Kai Shen - US grants

Loosely coupled distributed systems are those in which nodes can join, leave, or fail at high rates without centralized control and network connections or topology can be highly unstable. Examples include self-organizing overlay networks, mobile ad hoc networks (MANET), and sensor networks. This proposal seeks to address issues in supporting key searching in these dynamic systems. Keyword searching is an extremely effective utility for many higher-level distributed services, such as information retrieval in overlay networks and habitat monitoring for sensor networks.

This proposal seeks to build a distributed keyword searching framework that achieves a desirable level of system scalability, search speed, content staleness, and quality of search. The heart of the proposed design is a distributed data structure called a summary index, which maintains gradually less accurate search index for content farther away to achieve scalability. This project contains three main thrusts: 1. creating a robust "summary index"-based keyword searching framework for loosely coupled distributed systems, 2. examining the design of various system components and studying the tradeoffs among performance metrics, and 3. incorporating system integration and application studies.

Multi-core processors require increasingly sophisticated operating systems and middleware in order to ensure both security and performance isolation. Operating systems need to be aware of the on-chip resource requirements of individual threads and processes. Shared resources such as parts of the memory hierarchy and the off-chip bandwidth imply that interactions among concurrently executing processes might affect their performance and perceived priority. Resource-aware policies are imperative for improved performance, fairness, and scalability.

Some of the challenges faced in making the policies resource-aware include: identifying application resource requirements in a transparent manner, understanding the interactions among conflicting resource requirements, and enforcing the resource constraints in a manner that scales as the number of cores is increased. This research addresses these challenges by developing new system-level support for resource management in multi-core processors. The key idea is to use low-overhead hardware-provided statistics via counters as a mechanism to learn about resource requirements and conflicts without application involvement. Hardware counter statistics can also serve as a signature of program execution, benefiting tasks such as workload classification and phase change identification. At the level of the operating system, the project utilizes the online processor execution statistics to improve the efficiency and fairness of CPU scheduling and memory management, and manage the hardware-provided statistics as a first-class resource so that multiple applications can take advantage of the information.

By working with an existing open-source OS (Linux) and virtual machine monitor (Xen), the experimental work directly impacts today's multi-core users. Strong on-going collaborations with industry partners, in particular, IBM and Ask.com, permit this team to transfer technological advancements to mainstream processors and commercial applications. As one possible outcome, the hardware design of processor counters can be augmented to cooperate with the software system support. With a better understanding of software needs (for both statistics utilization and management), more informed tradeoffs can be made at the hardware level. The education component of this project will include direct research participation of both graduate and undergraduate students as well as curriculum enhancement for related systems courses. As a result, students will acquire valuable multidisciplinary (software/hardware) experience and training required to understand and advance increasingly complex future computer systems.

I/O performance is often an issue for high-end computing (HEC) codes, due to their increasingly data-intensive nature and the ever-growing CPU-I/O performance gap. Portable parallel I/O benchmarks can help
(1) application developers to improve their codes' performance,
(2) HEC storage systems architects to improve their designs, and
(3) future and current owners of HEC platforms to reduce hardware cost and improve application performance through better system provisioning and configuration.

To keep up with the growing scale and complexity of HEC applications, this project develops automated generation of parallel I/O benchmarks, analogous to the SPEC and NAS benchmarks for computation. Our approach will be embedded in BenchMaker, a prototype tool that takes a real-world, large-scale parallel application and automatically distills it into a compact, human-intelligible, I/O-intensive, and parameterized benchmark. Such a benchmark accurately reflects the original application's I/O characteristics and I/O performance, yet with shorter execution time, reduced need for libraries, better portability, and easy scalability.

Benchmarks and tools that benefit the computational science community at large will be produced by this research. These benchmark prototypes will be used for parallel computing course projects and student research contests.

The reliability, safety, and security of today's applications depend on controlled data accesses and updates during execution. For instance, many emerging applications are composed of multiple software modules. To protect these modules from each other within a single address space, inter-module operations need to be carefully monitored and controlled. Additionally, the reliability of online systems can benefit from live checking of memory access errors such as buffer overflows, memory leaks, and accesses to uninitialized data. Similarly, memory access monitoring can support information flow mtracking in a complex system for enhanced security.

Available mechanisms in today's processors are tied to support for virtual memory, making implementation of access control both heavy weight and coarse grained. The proposed research will design and utilize new light-weight memory access control mechanisms that are independent of and subordinate to existing system memory protection. At the hardware level, this approach minimizes impact on the processor core by placing the access control mechanisms outside the common critical path. At the operating system level, the required support is largely outside of the kernel memory management functions, incurring overhead only when exercised. Such auxiliary mechanisms are more amenable to practical deployment, yet they are capable of supporting fine-grained and flexible memory protection. In conjunction with these hardware/software mechanisms, the research will devise a new protection model that can be manipulated either at user or privileged level based on an application's requirements. The flexible, efficient memory monitoring framework developed will enable debugging tools that can help detect memory access errors such as out-of-bound accesses, and help enforce data security or privacy policies in live systems. The proposed work will target a wide variety of applications and utilizations with a view to validating the goal of improved programmer productivity.

Data-driven intelligence is an essential foundation for physical systems in transportation safety and efficiency, area surveillance and security, as well as environmental sustainability. This project develops new computer system infrastructure and algorithms for self-sustainable data-driven systems in the field. Research outcomes of the project include (a) a low-maintenance, environmentally-friendly hardware platform with solar energy harvesting and super capacitor-based energy storage, (b) virtualization software infrastructure for low-power nodes to enable inter-operability among distributed field nodes and from/to the data center, and (c) new image and data processing approaches for resource-adaptive fidelity adjustment and function partitioning. The synergy between the self-sustainable hardware, system software support, wireless communications management, and application data processing manifests through global coordination for quality-of-service, energy efficiency, and data privacy.

In broader impacts, this project enables data-driven intelligence in the field for important physical system domains. Integration of the technologies involved is accomplished through real-world system deployment and experimentation, including an intelligent campus traffic and parking management system and collaborative work with industry collaborators. The results of this project will further enhance the technological competitiveness for US industries in key areas such as intelligent transportation. The education component includes cross-disciplinary curriculum enhancements and the development of a new instructional platform for realistic experiments with cyber-physical systems. Within the scope of this project, the PIs perform mentoring and outreach activities to recruit/retain women and minorities in science and engineering.

The massive hardware scale, labyrinthine software complexity, and tangled external interactions of networked systems conspire to undermine reliability: Scale increases the frequency of failures while interconnectedness exacerbates their consequences by turning local mishaps into global disasters. This project will establish new system support toward recoverable network applications on two foundations. In an individual machine, fast, simple application recovery can be greatly eased if the application state on the persistent storage is kept always consistent. Over a networked system, the fault-tolerance and global consistency can be better supported and reasoned if application components commit local state before emitting any output to others. The time is right for this effort, because emerging Flash-based solid-state disks (SSDs) promise to dramatically reduce the cost of required persistent state management. Research will proceed along three fronts: First, the project will design and implement a new operating system mechanism (fast synchronous logging without double writes) for failure-atomic, synchronous I/O on SSDs. Second, for broad applicability, this project will present the programmers with simple extensions of familiar POSIX interfaces. Third, to achieve efficiency and fairness, research will develop a new I/O resource manager that combines the classic fair queuing scheduling with SSD-oriented anticipatory I/O. Fast, simple failure recovery mechanisms developed in this project will enable high reliability for a broad range of networked applications that are critical to today's digital economy and society. This project will also involve industry collaboration, curriculum enhancement, and student training.

This project investigates operating system mechanisms to manage hardware accelerator resources in a safe, fair, and protected manner while maintaining high performance. Programmable vector processors including general-purpose graphical processing units (GP-GPUs) and other accelerators for encryption, compression, media transcoding, pattern matching, parsing, etc. are increasingly ubiquitous in computer systems. For the sake of safety and fairness, such accelerators must be managed by the operating system, but for the sake of performance, they must be accessible directly from user-level applications, without OS intervention. The conflict between these goals is exacerbated by the opacity of proprietary library/driver/hardware interfaces. This project seeks a balanced solution to these conflicting goals through: (1) an operating system resource management architecture that allows direct user-level access in the common case, but intercedes in the existing accelerator access path when necessary to delay and re-order requests; (2) a tool chain that uncovers hidden interface semantics required for resource management, together with a characterization of the information needed from vendors in the future; and (3) an integrated management and scheduling strategy across the full set of computational resources in a given system.

By focusing on safe, fair, and efficient access to computational accelerators, the project aims to increase performance and power efficiency over a broad range of applications critical to today's digital economy and society. Broad dissemination is promoted through implementation in the Linux kernel, and open-source software release. Technology transfer is pursued through regular communication and collaboration with GPU industry vendors. Project research is integrated with education through curricular development and graduate student instruction.

Multicore systems-on-a-chip have permeated every segment of the
digital market, from servers and supercomputers, to desktops and smart
phone/mobile devices. Innovative applications continue to emerge that
integrate user interactivity via mobile devices with the power of
high-end computation and large-scale storage. These applications tend
to demonstrate dynamic and diverse execution behaviors, requiring
close tracking in order to manage resource consumption. Inherent
application behavior variations and resource requirements, coupled
with complex interactions due to contention for shared resources,
present new challenges for efficient, dependable, and sustainable
advances in computing and information technologies.

This project will develop foundational system mechanisms to manage
individual cores, memory, and power/energy consumption on
multicore-based systems, and explore resource allocation policies that
use these mechanisms. A new online multicore power model will allow
power and energy tracking at a fine-grain level, combining available
hardware-based power measurements with event-based modeling and
attribution of power for shared resources. Accuracy will be improved
via coarse-grain measurement-triggered online model recalibration. A
new operating system mechanism, power containers, will be developed to
allow application-defined boundaries for resource tracking, breaking
from the traditional thread and process boundary resource tracking in
state-of-the-art operating systems. Further optimizations will be
explored to lower the overhead of resource tracking, allowing online
power accounting to scale to large core and resource counts. Finally,
new techniques will be developed to enable use of the power containers
to control and isolate power usage in an application-defined manner.

This project will enhance the power protection, energy efficiency, and
dependability of multicore-based computer systems. The techniques
developed can be broadly applied to emerging dynamic applications in
data centers, desktops, and mobile devices. In particular, power
containers will identify and mitigate (either malicious or
unintentional) power anomalies (execution that results in unusually
high power consumption), in both high-end servers and multi-core and
multi-accelerator smart phones. The success of this project will
contribute to the long-term sustainability of the world's fast
evolving digital economy and society.

A memory device may exhibit errors due to manufacturing defects, device aging, or particle strikes from cosmic-ray-induced neutrons. Memory errors are an important threat to computer system reliability as semiconductor technologies continue to scale. This project develops a new approach that protects against memory errors non-uniformly by exploiting unequal error susceptibility at different memory regions in a computer system. Collaboration with industry researchers facilitates the integration of developed techniques into real-world memory technologies. Results of this project will contribute to comprehensive computer system reliability that is critical to society and the health of the world's economy. Curriculum enhancement and student training in this project enable advanced human resource development that is necessary for today's and tomorrow's digital workforce.

Research and development efforts within this project include four synergistic components: First, this project introduces a new software approach that systematically uncovers important characteristics of memory error propagation and its consequences. Second, research develops new energy-efficient hardware support for flexible, dynamic adjustment of memory error protection on each memory area. Third, this project devises non-uniform memory error protection policies that optimize for reliability and efficiency based on software error susceptibility and hardware protection costs. Finally, the developed error susceptibility assessment and non-uniform protection techniques are evaluated using real application scenarios. Cross-layer (software/hardware) technologies developed in this project enable wide utilization of advanced memory reliability mechanisms without significant loss of performance or energy efficiency.

? DESCRIPTION (provided by applicant): Cardiovascular diseases are the leading cause of death in the United States, and hypertension is an important risk factor for cardiovascular diseases. Mediated through cell-extracellular matrix contact, or focal adhesion, increased extracellular matrix stiffness causes aorta structural changes, thus contributes to hypertension development. It remains unclear how focal adhesion regulates responses of vascular smooth muscle cells to increased stiffness. The focal adhesion protein vinculin and its muscle specific splice variant metavinculin are the key components for force transmission. Therefore, our long-term research goal is to delineate the mechanism by which vascular smooth muscle cells respond to changes in extracellular matrix stiffness through metavinculin and vinculin. The goal of this proposal is to characterize metavinculin tail structural features important for actin cytoskeleton remodeling upon changes in extracellular matrix stiffness. Our hypothesis is that metavinculin C-terminal hairpin, released upon actin or phospholipid binding, binds toward vinculin tail C-terminal base to form a heterodimer, which is indispensable for bundling actin fibers in vascular smooth muscle cells. This hypothesis will be addressed using a combination of novel experimental and computational approaches with the following Specific Aims: (1) to characterize metavinculin and vinculin distribution in response to changes in substrate stiffness, (2) to determine the effect of metavinculin tail structure modification on the association of vinculin tail with actin and phospholipid, and (3) to determine metavinculin tail solution structur and locate metavinculin residues that are involved in actin induced metavinculin-vinculin heterodimer formation. Upon completion of the proposed work, we expect to define the role of metavinculin-vinculin heterodimer in cell cytoskeleton remodeling and build structural models for the heterodimer. The results of this study will help reveal vascular remodeling mechanism due to increased vascular stiffness and suggest new interventions to prevent hypertension development, and in turn help reduce morbidity, mortality, and disparity in cardiovascular diseases.

This award is supported by the Major Research Instrumentation and the Chemistry Research Instrumentation programs. Georgia Southern University (GSU) is acquiring a high-resolution, high-pressure, liquid chromatograph, quadrupole, time-of-flight mass spectrometer (HR-HPLC-Q-TOF-MS) to support Professor Nathaniel Shank and colleagues Mitch Weiland, Shainaz Landge, Gary Guillet and Kai Shen from Savannah State University (SSU). In general, mass spectrometry (MS) is one of the key analytical methods used to identify and characterize small quantities of chemical species embedded in complex samples. In a typical experiment, the components flow into a mass spectrometer where they are ionized and the ions' masses are measured. This highly sensitive technique allows the structure of molecules in complex mixtures to be studied. An instrument with a liquid chromatograph can separate mixtures of compounds before they reach the mass spectrometer. In the time-of-flight (TOF) method of mass spectrometry, the mass-to-charge ratio of an ion is determined by the way ions are accelerated by an electric field of known strength. The acquisition strengthens the research infrastructure at the University and regional area. The instrument broadens participation by involving diverse groups of students in research and research training using this modern analytical technique. It also provides training opportunities to many undergraduate students at these institution and serves as a resource for students to get hands-on exposure to advanced instrumentation resulting in a higher quality of education.

The award of the mass spectrometer is aimed at enhancing research and education at all levels. The instrument will be used for the development of peptide nucleic acid probes and the profiling Sigma-1 receptor metabolites which regulates calcium signaling in chaperone proteins. The instrumentation is used for characterizing air-sensitive transition metal complexes and developing ruthenium catalysts. In addition, it is used to identify oligonucleotide-protein conjugates. The mass spectrometer is utilized to analyze triazole based chemosensors and logic gates, as well as interface degradation. Finally, it is also utilized to characterize protein mimics and to identify chalcone analogues.

This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.