Jien-Chung Lo - US grants

Lo This research is on a class of concurrent error detecting (CED) methods for design in CMOS VLSI. The basis for the research is a novel built-in current sensor which is critical to new design methods for CED circuits in static CMOS. This technique is being applied to designs of floating point arithmetic units, processor control units, on-chip cache memories, and fast fourier transform processors. Algorithms for partitioning realistic faults into subsets, those that are detectable by the current sensor and those that are not, are being developed. New design rules for hardware redundancy are being explored.

9729839 Uht, Augustus K. University of Rhode Island Research Instrumentation: Equipment for Diverse Computer Architecture Research This research instrumentation grant enables three distinct research projects: - Realizing Instruction Level Parallelism in the 10's - A New Spectrum of Hierarchical Storage Architectures for High Performance Disk I/Os - Ultra-Dependable and High-Performance Distributed Computing while seeking to improve computer performance in many dimensions: uni- or micro-processors, I/O (Input/Output) systems, and multiple-computer systems. Further, the reliability of multiple-computer systems is to be enhanced. These objectives are to be achieved by using the new instrumentation equipment (multiprocessor and multiple-disk RAID storage system) in several different ways. First, the Levo research prototype uniprocessor is to be designed and simulated on the new multiprocessor. The latter will serve to verify Levo's implementation and measure its performance, as well as to allow Levo's construction, establishing that uniprocessors can be designed to execute an order-of-magnitude more instructions per cycle than current uniprocessors. Second, since I/O constraints can limit overall performance, the novel Disk Caching Disk (DCD) I/O system is to be realized on the new multiprocessor and RAID equipment, demonstrating factors of 2 to orders-of-magnitude performance improvements of the DCD architecture. Lastly, the Active Nodal Task Seeking (ANTS) distributed computing system achieves high performance and ultra-dependability in a coarse-grain environment. The new ANTS kernel is to be realized on the new multiprocessor, showing that the same can be achieved on fine-grain applications.

Modern IC's face many reliability problems and therefore online error detection mechanisms are necessary. Fault injection experiments are crucial in validating the correctness and in accessing the capability of these error handling or detecting designs. Prof. Lo is exploring the feasibility of using nanotechnology, specifically the nanofabrication of defects, in fault injection experiments. The faults are injected onto the silicon surfaces of commercial microprocessors/microcontrollers and FPGAs using the atomic force microscope (AFM)/scanning tunneling microscope (STM) with resolution down to hundreds of angstroms. The purpose is to create or at least emulate the effect of real-life run-time faults due to component aging, manufacture imperfections, electromigration and many others. Another goal of the project is to monitor the physical phenomena of the device under test. These include the power supply current level, thermal condition and electromagnetic activities. The proposed method is superior in that: (1) An accurate and repeatable fault injection experiment can be easily achieved; (2) The resolution of AFM/STM ranges from tens of micrometers to hundreds of angstroms; and (3) No radioactive material is involved