Samuel Palermo, Ph.D.
Affiliations: | 2007 | Stanford University, Palo Alto, CA |
Area:
Electrical Engineering, Computer scienceGoogle:
"Samuel Palermo"Mean distance: 7046.11
Parents
Sign in to add mentor| Mark Horowitz | grad student | 2007 | Stanford | |
| (Design of high-speed optical interconnect transceivers.) | ||||
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Publications
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| Entesari K, Palermo S, Madsen C, et al. (2020) Silicon Photonics for Microwave Applications: Programmable Filters and Beamformers Ieee Microwave Magazine. 21: 20-42 |
| Fan Y, Kumar A, Iwai T, et al. (2020) A 32-Gb/s Simultaneous Bidirectional Source-Synchronous Transceiver With Adaptive Echo Cancellation Techniques Ieee Journal of Solid-State Circuits. 55: 439-451 |
| Wang B, Huang Q, Chen K, et al. (2019) MODULATION ON SILICON FOR DATACOM: PAST, PRESENT, AND FUTURE (INVITED REVIEW) Progress in Electromagnetics Research. 166: 119-145 |
| Kiran S, Shafik A, Tabasy EZ, et al. (2019) Modeling of ADC-Based Serial Link Receivers With Embedded and Digital Equalization Ieee Transactions On Components, Packaging and Manufacturing Technology. 9: 536-548 |
| Kiran S, Cai S, Zhu Y, et al. (2019) Digital Equalization With ADC-Based Receivers: Two Important Roles Played by Digital Signal Processingin Designing Analog-to-Digital-Converter-Based Wireline Communication Receivers Ieee Microwave Magazine. 20: 62-79 |
| Palermo S, Sun N. (2019) Introduction to the Special Section on the 2018 Custom Integrated Circuits Conference Ieee Journal of Solid-State Circuits. 54: 611-612 |
| Roshan-Zamir A, Iwai T, Fan Y, et al. (2019) A 56-Gb/s PAM4 Receiver With Low-Overhead Techniques for Threshold and Edge-Based DFE FIR- and IIR-Tap Adaptation in 65-nm CMOS Ieee Journal of Solid-State Circuits. 54: 672-684 |
| Kiran S, Cai S, Luo Y, et al. (2019) A 52-Gb/s ADC-Based PAM-4 Receiver With Comparator-Assisted 2-bit/Stage SAR ADC and Partially Unrolled DFE in 65-nm CMOS Ieee Journal of Solid-State Circuits. 54: 659-671 |
| Palermo S, Hoyos S, Cai S, et al. (2018) Analog-to-Digital Converter-Based Serial Links: An Overview Ieee Solid-State Circuits Magazine. 10: 35-47 |
| Tyagi A, Iwai T, Yu K, et al. (2018) A 50 Gb/s PAM-4 VCSEL Transmitter With 2.5-Tap Nonlinear Equalization in 65-nm CMOS Ieee Photonics Technology Letters. 30: 1246-1249 |