Dinesh Patil, Ph.D.
Affiliations: | 2008 | Stanford University, Palo Alto, CA |
Area:
Electrical Engineering, Computer scienceGoogle:
"Dinesh Patil"Mean distance: 7046.11
Parents
Sign in to add mentor| Mark Horowitz | grad student | 2008 | Stanford | |
| (Design of robust energy-efficient digital circuits using geometric programming.) | ||||
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Publications
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| Zheng X, Patil D, Lexau J, et al. (2011) Ultra-efficient 10 Gb/s hybrid integrated silicon photonic transmitter and receiver. Optics Express. 19: 5172-86 |
| Zheng X, Liu F, Patil D, et al. (2010) A sub-picojoule-per-bit CMOS photonic receiver for densely integrated systems. Optics Express. 18: 204-11 |
| Morifuji E, Patil D, Horowitz M, et al. (2007) Power Optimization for SRAM and Its Scaling Ieee Transactions On Electron Devices. 54: 715-722 |