Hayden K. So, Ph.D.
Affiliations: | 2007 | University of California, Berkeley, Berkeley, CA, United States |
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Parents
Sign in to add mentor| Robert W. Brodersen | grad student | 2007 | UC Berkeley | |
| (BORPH: An operating system for FPGA-based reconfigurable computers.) | ||||
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Publications
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| Wang M, Lee KCM, Chung BMF, et al. (2021) Low-Latency In Situ Image Analytics With FPGA-Based Quantized Convolutional Neural Network. Ieee Transactions On Neural Networks and Learning Systems |
| Shi R, Wong JSJ, So HK. (2019) High-Throughput Line Buffer Microarchitecture for Arbitrary Sized Streaming Image Processing Journal of Imaging. 5: 34 |
| Engelhardt N, So HK. (2019) GraVF-M: Graph Processing System Generation for Multi-FPGA Platforms Acm Transactions On Reconfigurable Technology and Systems. 12: 1-28 |
| Jaiswal MK, So HK. (2019) Design of quadruple precision multiplier architectures with SIMD single and double precision support Integration. 65: 163-174 |
| So HK, Gross WJ. (2018) Introduction to the Special Issue on Application-Specific Systems, Architectures and Processors Journal of Signal Processing Systems. 90: 1-2 |
| Jaiswal MK, So HK. (2018) An Unified Architecture for Single, Double, Double-Extended, and Quadruple Precision Division Circuits Systems and Signal Processing. 37: 383-407 |
| Engelhardt N, So HK. (2017) Towards Flexible Automatic Generation of Graph Processing Gateware Heart. 5 |
| Lin CY, Jiang Z, Fu C, et al. (2017) FPGA High-level Synthesis versus Overlay: Comparisons on Computation Kernels Acm Sigarch Computer Architecture News. 44: 92-97 |
| Jaiswal MK, So HK. (2017) Area-Efficient Architecture for Dual-Mode Double Precision Floating Point Division Ieee Transactions On Circuits and Systems I-Regular Papers. 64: 386-398 |
| Lin CY, Wong N, So HK. (2013) Design space exploration for sparse matrix‐matrix multiplication on FPGAs International Journal of Circuit Theory and Applications. 41: 205-219 |