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Hojin Kee, Ph.D. - Publications

Affiliations: 
2010 Electrical Engineering University of Maryland, College Park, College Park, MD 
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11 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2017 Mhaske S, Kee H, Ly T, Aziz A, Spasojevic P. FPGA-Based Channel Coding Architectures for 5G Wireless Using High-Level Synthesis International Journal of Reconfigurable Computing. 2017: 1-23. DOI: 10.1155/2017/3689308  0.456
2016 Mhaske S, Kee H, Ly T, Aziz A, Spasojevic P. High-throughput FPGA-based QC-LDPC decoder architecture 2015 Ieee 82nd Vehicular Technology Conference, Vtc Fall 2015 - Proceedings. DOI: 10.1109/VTCFall.2015.7390967  0.307
2014 Wu H, Shen C, Kee H, Sane N, Plishker W, Bhattacharyya SS. Mapping Parameterized Dataflow Graphs onto FPGA Platforms Academic Press Library in Signal Processing. 4: 643-673. DOI: 10.1016/B978-0-12-396501-1.00024-8  0.665
2012 Kee H, Shen CC, Bhattacharyya SS, Wong I, Rao Y, Kornerup J. Mapping parameterized cyclo-static dataflow graphs onto configurable hardware Journal of Signal Processing Systems. 66: 285-301. DOI: 10.1007/s11265-011-0599-5  0.628
2011 Sane N, Kee H, Seetharaman G, Bhattacharyya SS. Topological patterns for scalable representation and analysis of dataflow graphs Journal of Signal Processing Systems. 65: 229-244. DOI: 10.1007/s11265-011-0610-1  0.697
2010 Sane N, Kee H, Seetharaman G, Bhattacharyya SS. Scalable representation of dataflow graph structures using topological patterns Ieee Workshop On Signal Processing Systems, Sips: Design and Implementation. 13-18. DOI: 10.1109/SIPS.2010.5624821  0.699
2010 Wu HH, Kee H, Sane N, Plishker W, Bhattacharyya SS. Rapid prototyping for digital signal processing systems using parameterized synchronous dataflow graphs Proceedings of the International Workshop On Rapid System Prototyping. DOI: 10.1109/RSP.2010.5656423  0.701
2010 Kee H, Bhattacharyya SS, Kornerup J. Efficient static buffering to guarantee throughput-optimal FPGA implementation of synchronous dataflow graphs Proceedings - 2010 International Conference On Embedded Computer Systems: Architectures, Modeling and Simulation, Ic-Samos 2010. 136-143. DOI: 10.1109/ICSAMOS.2010.5642074  0.618
2010 Kee H, Bhattacharyya SS, Wong I, Rao Y. FPGA-based design and implementation of the 3GPP-LTE physical layer using parameterized synchronous dataflow techniques Icassp, Ieee International Conference On Acoustics, Speech and Signal Processing - Proceedings. 1510-1513. DOI: 10.1109/ICASSP.2010.5495504  0.624
2009 Kee H, Bhattacharyya SS, Petersen N, Kornerup J. Resource-efficient acceleration of 2-dimensional Fast Fourier Transform computations on FPGAs 2009 3rd Acm/Ieee International Conference On Distributed Smart Cameras, Icdsc 2009. DOI: 10.1109/ICDSC.2009.5289356  0.495
2008 Kee H, Petersen N, Kornerup J, Bhattacharyya SS. Systematic generation of FPGA-based FFT implementations Icassp, Ieee International Conference On Acoustics, Speech and Signal Processing - Proceedings. 1413-1416. DOI: 10.1109/ICASSP.2008.4517884  0.545
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