Year |
Citation |
Score |
2020 |
Pal S, Petrisko D, Kumar R, Gupta P. Design Space Exploration for Chiplet-Assembly-Based Processors Ieee Transactions On Very Large Scale Integration Systems. 28: 1062-1073. DOI: 10.1109/Tvlsi.2020.2968904 |
0.345 |
|
2020 |
Chu E, Luo Y, Gupta P. Design Impacts of Back-End-of-Line Line Edge Roughness Ieee Transactions On Semiconductor Manufacturing. 33: 32-41. DOI: 10.1109/Tsm.2019.2953864 |
0.364 |
|
2019 |
Gupta P, Iyer SS. Goodbye, motherboard. Bare chiplets bonded to silicon will make computers smaller and more powerful: Hello, silicon-interconnect fabric Ieee Spectrum. 56: 28-33. DOI: 10.1109/Mspec.2019.8847587 |
0.31 |
|
2019 |
Gupta RK, Mitra S, Gupta P. Variability Expeditions: A Retrospective Ieee Design & Test of Computers. 36: 65-67. DOI: 10.1109/Mdat.2018.2889103 |
0.334 |
|
2018 |
Wang W, Yona Y, Diggavi SN, Gupta P. Design and Analysis of Stability-Guaranteed PUFs Ieee Transactions On Information Forensics and Security. 13: 978-992. DOI: 10.1109/Tifs.2017.2774761 |
0.332 |
|
2018 |
Wang S, Lee H, Grezes C, Amiri P, Wang K, Gupta P. Adaptive MRAM Write and Read with MTJ Variation Monitor Ieee Transactions On Emerging Topics in Computing. 1-1. DOI: 10.1109/Tetc.2018.2866289 |
0.325 |
|
2018 |
Wang W, Zhao C, Gupta P. Assessing Layout Density Benefits of Vertical Channel Devices Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 37: 3211-3215. DOI: 10.1109/Tcad.2017.2782758 |
0.303 |
|
2017 |
Gottscho M, Alam I, Schoeny C, Dolecek L, Gupta P. Low-Cost Memory Fault Tolerance for IoT Devices Acm Transactions in Embedded Computing Systems. 16: 128. DOI: 10.1145/3126534 |
0.307 |
|
2017 |
Badr Y, Gupta P. Technology path-finding for directed self-assembly for via layers Proceedings of Spie. 10148. DOI: 10.1117/12.2257821 |
0.324 |
|
2017 |
Badr YA, Gupta P. Technology path-finding framework for directed-self assembly for via layers Journal of Micro-Nanolithography Mems and Moems. 16: 13505-13505. DOI: 10.1117/1.Jmm.16.1.013505 |
0.323 |
|
2017 |
Wang S, Pan A, Grezes C, Amiri PK, Wang KL, Chui CO, Gupta P. Leveraging nMOS Negative Differential Resistance for Low Power, High Reliability Magnetic Memory Ieee Transactions On Electron Devices. 64: 4084-4090. DOI: 10.1109/Ted.2017.2742500 |
0.306 |
|
2017 |
Wang S, Pan A, Chui CO, Gupta P. Tunneling Negative Differential Resistance-Assisted STT-RAM for Efficient Read and Write Operations Ieee Transactions On Electron Devices. 64: 121-129. DOI: 10.1109/Ted.2016.2631544 |
0.35 |
|
2017 |
Chan T, Gupta P, Han K, Kagalwalla AA, Kahng AB. Benchmarking of Mask Fracturing Heuristics Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 36: 170-183. DOI: 10.1109/Tcad.2016.2620902 |
0.736 |
|
2017 |
Badr Y, Torres A, Gupta P. Mask Assignment and DSA Grouping for DSA-MP Hybrid Lithography for Sub-7 nm Contact/Via Holes Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 36: 913-926. DOI: 10.1109/Tcad.2016.2614262 |
0.321 |
|
2017 |
Zhu L, Badr Y, Wang S, Iyer S, Gupta P. Assessing Benefits of a Buried Interconnect Layer in Digital Designs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 36: 346-350. DOI: 10.1109/Tcad.2016.2572144 |
0.326 |
|
2017 |
Grezes C, Lee H, Lee A, Wang S, Ebrahimi F, Li X, Wong K, Katine JA, Ocker B, Langer J, Gupta P, Amiri PK, Wang KL. Write Error Rate and Read Disturbance in Electric-Field-Controlled Magnetic Random-Access Memory Ieee Magnetics Letters. 8: 1-5. DOI: 10.1109/Lmag.2016.2630667 |
0.306 |
|
2017 |
Lai L, Gupta P. System-Level Dynamic Variation Margining in Presence of Monitoring and Actuation Ieee Embedded Systems Letters. 9: 85-88. DOI: 10.1109/Les.2017.2716918 |
0.34 |
|
2016 |
Wang S, Pan A, Chui CO, Gupta P. PROCEED: A Pareto Optimization-Based Circuit-Level Evaluator for Emerging Devices Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 24: 192-205. DOI: 10.1109/Tvlsi.2015.2393852 |
0.367 |
|
2016 |
Lee H, Grezes C, Wang S, Ebrahimi F, Gupta P, Amiri PK, Wang KL. Source Line Sensing in Magneto-Electric Random-Access Memory to Reduce Read Disturbance and Improve Sensing Margin Ieee Magnetics Letters. 7: 1-5. DOI: 10.1109/Lmag.2016.2552149 |
0.309 |
|
2016 |
Wang S, Lee H, Ebrahimi F, Amiri PK, Wang KL, Gupta P. Comparative Evaluation of Spin-Transfer-Torque and Magnetoelectric Random Access Memory Ieee Journal On Emerging and Selected Topics in Circuits and Systems. DOI: 10.1109/Jetcas.2016.2547681 |
0.311 |
|
2015 |
Gottscho M, BanaiyanMofrad A, Dutt N, Nicolau A, Gupta P. DPCS Acm Transactions On Architecture and Code Optimization. 12: 1-26. DOI: 10.1145/2792982 |
0.323 |
|
2015 |
Badr Y, Torres JA, Ma Y, Mitra J, Gupta P. Incorporating DSA in multipatterning semiconductor manufacturing technologies Proceedings of Spie - the International Society For Optical Engineering. 9427. DOI: 10.1117/12.2084776 |
0.354 |
|
2015 |
Leung G, Wang S, Pan A, Gupta P, Chui CO. An Evaluation Framework for Nanotransfer Printing-Based Feature-Level Heterogeneous Integration in VLSI Circuits Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. DOI: 10.1109/Tvlsi.2015.2477282 |
0.368 |
|
2014 |
Kagalwalla AA, Gupta P. Comprehensive defect avoidance framework for mitigating EUV mask defects Proceedings of Spie - the International Society For Optical Engineering. 9048. DOI: 10.1117/12.2046701 |
0.737 |
|
2014 |
Badr Y, Ma K, Gupta P. Layout pattern-driven design rule evaluation Proceedings of Spie. 9053: 905307. DOI: 10.1117/12.2046140 |
0.348 |
|
2014 |
Badr YA, Ma K, Gupta P. Layout pattern-driven design rule evaluation Journal of Micro-Nanolithography Mems and Moems. 13: 43018-43018. DOI: 10.1117/1.Jmm.13.4.043018 |
0.332 |
|
2014 |
Kagalwalla AA, Gupta P. Comprehensive defect avoidance framework for mitigating extreme ultraviolet mask defects Journal of Micro/ Nanolithography, Mems, and Moems. 13. DOI: 10.1117/1.Jmm.13.4.043005 |
0.741 |
|
2014 |
Chan T, Gupta P, Kahng AB, Lai L. Synthesis and Analysis of Design-Dependent Ring Oscillator (DDRO) Performance Monitors Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 22: 2117-2130. DOI: 10.1109/Tvlsi.2013.2282742 |
0.496 |
|
2014 |
Lai L, Chandra V, Aitken RC, Gupta P. SlackProbe: A Flexible and Efficient In Situ Timing Slack Monitoring Methodology Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 33: 1168-1179. DOI: 10.1109/Tcad.2014.2323195 |
0.359 |
|
2014 |
Lai L, Chandra V, Aitken R, Gupta P. BTI-Gater: An Aging-Resilient Clock Gating Methodology Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 4: 180-189. DOI: 10.1109/Jetcas.2014.2315882 |
0.333 |
|
2014 |
Cheng L, Xu W, Ren F, Gong F, Gupta P, He L. Statistical timing and power analysis of VLSI considering non-linear dependence Integration, the Vlsi Journal. 47: 487-498. DOI: 10.1016/J.Vlsi.2013.12.004 |
0.44 |
|
2013 |
Lee J, Gupta P. ECO cost measurement and incremental gate sizing for late process changes Acm Transactions On Design Automation of Electronic Systems. 18: 16. DOI: 10.1145/2390191.2390207 |
0.35 |
|
2013 |
Mok S, Lee J, Gupta P. Discrete sizing for leakage power optimization in physical design: A comparative study Acm Transactions On Design Automation of Electronic Systems. 18: 15. DOI: 10.1145/2390191.2390206 |
0.329 |
|
2013 |
Ghaida RS, Gupta M, Gupta P. A framework for exploring the interaction between design rules and overlay control Proceedings of Spie. 8681. DOI: 10.1117/12.2013619 |
0.361 |
|
2013 |
Ghaida RS, Gupta M, Gupta P. Framework for exploring the interaction between design rules and overlay control Journal of Micro-Nanolithography Mems and Moems. 12: 33014-33014. DOI: 10.1117/1.Jmm.12.3.033014 |
0.363 |
|
2013 |
Wanner L, Apte C, Balani R, Gupta P, Srivastava M. Hardware variability-aware duty cycling for embedded sensors Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 21: 1000-1012. DOI: 10.1109/Tvlsi.2012.2203325 |
0.307 |
|
2013 |
Kagalwalla AA, Gupta P. Design-aware defect-avoidance floorplanning of EUV masks Ieee Transactions On Semiconductor Manufacturing. 26: 111-124. DOI: 10.1109/Tsm.2012.2234151 |
0.755 |
|
2013 |
Wang S, Leung G, Pan A, Chui CO, Gupta P. Evaluation of digital circuit-level variability in inversion-mode and junctionless FinFET technologies Ieee Transactions On Electron Devices. 60: 2186-2193. DOI: 10.1109/Ted.2013.2264937 |
0.37 |
|
2013 |
Ghaida RS, Agarwal KB, Nassif SR, Yuan X, Liebmann LW, Gupta P. Layout decomposition and legalization for double-patterning technology Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 32: 202-215. DOI: 10.1109/Tcad.2012.2232710 |
0.368 |
|
2013 |
Gupta P, Agarwal Y, Dolecek L, Dutt N, Gupta RK, Kumar R, Mitra S, Nicolau A, Rosing TS, Srivastava MB, Swanson S, Sylvester D. Underdesigned and opportunistic computing in presence of hardware variability Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 32: 8-23. DOI: 10.1109/Tcad.2012.2223467 |
0.337 |
|
2012 |
Lee J, Gupta P. Discrete Circuit Optimization: Library Based Gate Sizing and Threshold Voltage Assignment Foundations and Trends in Electronic Design Automation. 6: 1-120. DOI: 10.1561/9781601985439 |
0.348 |
|
2012 |
Kagalwalla AA, Muddu S, Capodieci L, Zelnik C, Gupta P. Design-of-experiments based design rule optimization Proceedings of Spie - the International Society For Optical Engineering. 8327. DOI: 10.1117/12.918067 |
0.744 |
|
2012 |
Ghaida RS, Agarwal KB, Liebmann LW, Nassif SR, Gupta P. A novel methodology for triple/multiple-patterning layout decomposition Proceedings of Spie - the International Society For Optical Engineering. 8327. DOI: 10.1117/12.916636 |
0.33 |
|
2012 |
Pant A, Gupta P, Van Der Schaar M. AppAdapt: Opportunistic application adaptation in presence of hardware variation Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 20: 1986-1996. DOI: 10.1109/Tvlsi.2011.2167360 |
0.33 |
|
2012 |
Chan T, Pant A, Cheng L, Gupta P. Design-Dependent Process Monitoring for Wafer Manufacturing and Test Cost Reduction Ieee Transactions On Semiconductor Manufacturing. 25: 447-459. DOI: 10.1109/Tsm.2012.2196709 |
0.36 |
|
2012 |
Leung G, Lai L, Gupta P, Chui CO. Device- and circuit-level variability caused by line edge roughness for sub-32-nm FinFET technologies Ieee Transactions On Electron Devices. 59: 2057-2063. DOI: 10.1109/Ted.2012.2199499 |
0.338 |
|
2012 |
Ghaida RS, Gupta P. DRE: A Framework for Early Co-Evaluation of Design Rules, Technology Choices, and Layout Methodologies Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 1379-1392. DOI: 10.1109/Tcad.2012.2192477 |
0.359 |
|
2012 |
Kagalwalla AA, Gupta P, Progler CJ, McDonald S. Design-aware mask inspection Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 690-702. DOI: 10.1109/Tcad.2011.2181909 |
0.749 |
|
2012 |
Gottscho M, Kagalwalla AA, Gupta P. Power variability in contemporary DRAMs Ieee Embedded Systems Letters. 4: 37-40. DOI: 10.1109/Les.2012.2192414 |
0.709 |
|
2011 |
Kulkarni P, Gupta P, Ercegovac MD. Trading accuracy for power in a multiplier architecture Journal of Low Power Electronics. 7: 490-501. DOI: 10.1166/Jolpe.2011.1157 |
0.364 |
|
2011 |
Kagalwalla AA, Gupta P, Hur DH, Park CH. Defect-aware reticle floorplanning for EUV masks Proceedings of Spie - the International Society For Optical Engineering. 7974. DOI: 10.1117/12.881667 |
0.751 |
|
2011 |
Chan TB, Kagalwalla AA, Gupta P. Measurement and optimization of electrical process window Journal of Micro/Nanolithography, Mems, and Moems. 10. DOI: 10.1117/1.3545822 |
0.741 |
|
2011 |
Ghaida RS, Torres G, Gupta P. Single-Mask Double-Patterning Lithography for Reduced Cost and Improved Overlay Control Ieee Transactions On Semiconductor Manufacturing. 24: 93-103. DOI: 10.1109/Tsm.2010.2076305 |
0.349 |
|
2011 |
Cheng L, Gupta P, Spanos CJ, Qian K, He L. Physically justifiable die-level modeling of spatial variation in view of systematic across wafer variability Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 30: 388-401. DOI: 10.1109/Tcad.2010.2089568 |
0.412 |
|
2010 |
Gupta P. What is process window Acm Sigda Newsletter. 40: 1-1. DOI: 10.1145/1866975.1866976 |
0.305 |
|
2010 |
Chan T, Kagalwalla AA, Gupta P. Measurement and optimization of electrical process window Proceedings of Spie. 7641. DOI: 10.1117/12.849066 |
0.738 |
|
2010 |
Ghaida RS, Gupta P. Within-Layer Overlay Impact for Design in Metal Double Patterning Ieee Transactions On Semiconductor Manufacturing. 23: 381-390. DOI: 10.1109/Tsm.2010.2050157 |
0.349 |
|
2010 |
Cong J, Gupta P, Lee J. Evaluating Statistical Power Optimization Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 29: 1750-1762. DOI: 10.1109/Tcad.2010.2061390 |
0.361 |
|
2009 |
Ghaida RS, Gupta P. Design-overlay interactions in metal double patterning Proceedings of Spie. 7275: 727514. DOI: 10.1117/12.814299 |
0.348 |
|
2009 |
Cheng L, Gupta P, He L. Efficient Additive Statistical Leakage Estimation Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 28: 1777-1781. DOI: 10.1109/Tcad.2009.2030433 |
0.469 |
|
2008 |
Gupta P, Kahng AB, Kim Y, Shah S, Sylvester D. Shaping Gate Channels for Improved Devices Proceedings of Spie. 6925. DOI: 10.1117/12.772889 |
0.548 |
|
2007 |
Gupta P, Kahng AB, Chul-Hong P. Detailed Placement for Enhanced Control of Resist and Etch CDs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 2144-2157. DOI: 10.1109/Tcad.2007.906998 |
0.541 |
|
2007 |
Gupta P, Kahng AB, Kim Y, Sylvester D. Self-Compensating Design for Reduction of Timing and Leakage Sensitivity to Systematic Pattern-Dependent Variation Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 1614-1624. DOI: 10.1109/Tcad.2007.895759 |
0.569 |
|
2006 |
Gupta P, Kahng AB, Park C, Samadi K, Xu X. Wafer Topography-Aware Optical Proximity Correction Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 2747-2756. DOI: 10.1109/Tcad.2006.882604 |
0.576 |
|
2006 |
Gupta P, Kahng A, Sharma P, Sylvester D. Gate-length biasing for runtime-leakage control Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 1475-1485. DOI: 10.1109/Tcad.2005.857313 |
0.578 |
|
2005 |
Gupta P, Kahng AB, Mantik S. Routing-aware scan chain ordering Acm Transactions On Design Automation of Electronic Systems. 10: 546-560. DOI: 10.1145/1080334.1080339 |
0.737 |
|
Show low-probability matches. |