Year |
Citation |
Score |
2016 |
Savoj H, Mishchenko A, Brayton R. ${m}$ -Inductive Property of Sequential Circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 35: 919-930. DOI: 10.1109/Tcad.2015.2481860 |
0.338 |
|
2014 |
Karthik AV, Soloveichik D, Ray S, Sterin B, Mishchenko A, Brayton R, Roychowdhury J. NINJA: Boolean modelling and formal verification of tiered-rate chemical reaction networks (Extended Abstract) Acm Bcb 2014 - 5th Acm Conference On Bioinformatics, Computational Biology, and Health Informatics. 623-624. DOI: 10.1145/2649387.2660805 |
0.423 |
|
2014 |
Savoj H, Mishchenko A, Brayton R. Sequential equivalence checking for clock-gated circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 33: 305-317. DOI: 10.1109/Tcad.2013.2284190 |
0.418 |
|
2014 |
Karthik AV, Ray S, Nuzzo P, Mishchenko A, Brayton R, Roychowdhury J. ABCD-NL: Approximating Continuous non-linear dynamical systems using purely Boolean models for analog/mixed-signal verification Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 250-255. DOI: 10.1109/ASPDAC.2014.6742898 |
0.493 |
|
2014 |
Long J, Brayton RK, Case M. LEC: Learning-driven data-path equivalence checking Ceur Workshop Proceedings. 1130: 9-18. |
0.589 |
|
2013 |
Mishchenko A, Een N, Brayton R, Case M, Chauhan P, Sharma N. A semi-canonical form for sequential AIGs Proceedings -Design, Automation and Test in Europe, Date. 797-802. |
0.609 |
|
2011 |
Yang YS, Sinha S, Veneris A, Brayton RK. Automating logic transformations with approximate SPFDs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 30: 651-664. DOI: 10.1109/Tcad.2011.2110590 |
0.366 |
|
2011 |
Yang YS, Sinha S, Veneris A, Brayton R, Smith D. Automated logic restructuring with aSPFDs Advanced Techniques in Logic Synthesis, Optimizations and Applications. 267-286. DOI: 10.1007/978-1-4419-7518-8_15 |
0.302 |
|
2010 |
Brayton R, Cong J. NSF workshop on EDA: Past, present, and future (Part 2) Ieee Design and Test of Computers. 27: 62-74. DOI: 10.1109/Mdt.2010.70 |
0.301 |
|
2010 |
Savoj H, Berthelot D, Mishchenko A, Brayton R. Combinational techniques for sequential equivalence checking Formal Methods in Computer Aided Design, Fmcad 2010. 145-149. |
0.309 |
|
2008 |
Mishchenko A, Case M, Brayton R, Stephen J. Scalable and scalably-verifiable sequential synthesis Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 234-241. DOI: 10.1109/ICCAD.2008.4681580 |
0.656 |
|
2008 |
Case ML, Mishchenko A, Brayton RK, Baumgartner J, Mony H. Invariant-strengthened elimination of dependent state elements Proceedings of the 2008 International Conference On Formal Methods in Computer-Aided Design, Fmcad. DOI: 10.1109/FMCAD.2008.ECP.6 |
0.665 |
|
2008 |
Case ML, Kravets VN, Mishchenko A, Brayton RK. Merging nodes under sequential observability Proceedings - Design Automation Conference. 540-545. DOI: 10.1109/DAC.2008.4555875 |
0.665 |
|
2008 |
Hurst AP, Mishchenko A, Brayton RK. Scalable min-register retiming under timing and initializability constraints Proceedings - Design Automation Conference. 534-539. DOI: 10.1109/DAC.2008.4555874 |
0.764 |
|
2008 |
Yevtushenko N, Villa T, Brayton RK, Petrenko A, Sangiovanni-Vincentelli AL. Compositionally progressive slutions of synchronous FSM equations Discrete Event Dynamic Systems: Theory and Applications. 18: 51-89. DOI: 10.1007/S10626-007-0031-2 |
0.522 |
|
2007 |
Villa T, Zharikova S, Yevtushenko N, Brayton R, Sangiovanni-Vincentelli A. A new algorithm for the largest compositionally progressive solution of synchronous language equations Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 441-444. DOI: 10.1145/1228784.1228888 |
0.462 |
|
2007 |
Mishchenko A, Chatterjee S, Brayton RK. Improvements to technology mapping for LUT-based FPGAs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 240-253. DOI: 10.1109/Tcad.2006.887925 |
0.521 |
|
2007 |
Hurst AP, Mishchenko A, Brayton RK. Fast minimum-register retiming via binary maximum-flow Proceedings - Formal Methods in Computer Aided Design, Fmcad 2007. 181-187. DOI: 10.1109/FAMCAD.2007.31 |
0.749 |
|
2007 |
Case ML, Mishchenko A, Brayton RK. Automated extraction of inductive invariants to aid model checking Proceedings - Formal Methods in Computer Aided Design, Fmcad 2007. 165-172. DOI: 10.1109/FAMCAD.2007.12 |
0.66 |
|
2006 |
Jiang JHR, Brayton RK. Retiming and resynthesis: A complexity perspective Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 2674-2686. DOI: 10.1109/Tcad.2006.882520 |
0.38 |
|
2006 |
Chatterjee S, Mishchenko A, Brayton RK, Wang X, Kam T. Reducing structural bias in technology mapping Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 2894-2902. DOI: 10.1109/Tcad.2006.882484 |
0.523 |
|
2006 |
Mishchenko A, Zhang JS, Sinha S, Burch JR, Brayton R, Chrzanowska-Jeske M. Using simulation and satisfiability to compute flexibilities in Boolean networks Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 743-754. DOI: 10.1109/Tcad.2005.860955 |
0.33 |
|
2004 |
Khatri SP, Sinha S, Brayton RK, Sangiovanni-Vincentelli AL. SPFD-based wire removal in standard-cell and network-of-PLA circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 23: 1020-1030. DOI: 10.1109/Tcad.2004.829821 |
0.723 |
|
2003 |
Singhal V, Pixley C, Aziz A, Qadeer S, Brayton R. Sequential optimization in the absence of global reset Acm Transactions On Design Automation of Electronic Systems. 8: 222-251. DOI: 10.1145/762488.762493 |
0.404 |
|
2003 |
Mo F, Brayton R. PLA-based regular structures and their synthesis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 22: 723-729. DOI: 10.1109/Tcad.2003.811454 |
0.571 |
|
2003 |
Jiang JHR, Brayton RK. On the verification of sequential equivalence Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 22: 686-697. DOI: 10.1109/Tcad.2003.811446 |
0.323 |
|
2003 |
Yevtushenko N, Villa T, Brayton RK, Petrenko A, Sangiovanni-Vincentelli AL. Equisolvability of series vs. controller's topology in synchronous language equations Proceedings -Design, Automation and Test in Europe, Date. 1154-1155. DOI: 10.1109/DATE.2003.1253778 |
0.439 |
|
2002 |
Sinha S, Mishchenko A, Brayton RK. Topologically constrained logic synthesis Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 679-686. DOI: 10.1145/774572.774672 |
0.327 |
|
2002 |
Goldberg EI, Prasad MR, Brayton RK. Using problem symmetry in search based satisfiability algorithms Proceedings -Design, Automation and Test in Europe, Date. 134-141. DOI: 10.1109/DATE.2002.998261 |
0.572 |
|
2002 |
Aziz A, Shiple T, Singhal V, Brayton R, Sangiovanni-Vincentelli A. Formula-dependent equivalence for compositional CTL model checking Formal Methods in System Design. 21: 193-224. DOI: 10.1023/A:1016043502772 |
0.466 |
|
2001 |
Goldberg EI, Prasad MR, Brayton RK. Using SAT for combinational equivalence checking Proceedings -Design, Automation and Test in Europe, Date. 114-121. DOI: 10.1109/DATE.2001.915010 |
0.59 |
|
2001 |
Singhal V, Pixley C, Aziz A, Brayton RK. Theory of safe replacements for sequential circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 20: 249-265. DOI: 10.1109/43.908455 |
0.324 |
|
2001 |
Yevtushenko N, Villa T, Brayton RK, Petrenko A, Sangiovanni-Vincentelli AL. Solution of parallel language equations for logic synthesis Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 103-110. |
0.458 |
|
2000 |
Aziz A, Sanwal K, Singhal V, Brayton R. Model-checking continuous-time Markov chains Acm Transactions On Computational Logic. 1: 162-170. DOI: 10.1145/343369.343402 |
0.33 |
|
2000 |
Goldberg EI, Carloni LP, Villa T, Brayton RK. Negative thinking in branch-and-bound: the case of unate covering Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 19: 281-294. DOI: 10.1109/43.833198 |
0.388 |
|
2000 |
Tabbara A, Tabbara B, Brayton RK, Newton RA. Integration of retiming with architectural floorplanning Integration, the Vlsi Journal. 29: 25-43. DOI: 10.1016/S0167-9260(99)00021-8 |
0.432 |
|
1999 |
Ranjan RK, Singhal V, Somenzi F, Brayton RK. Using combinational verification for sequential circuits Proceedings -Design, Automation and Test in Europe, Date. 138-144. DOI: 10.1109/DATE.1999.761109 |
0.308 |
|
1999 |
Carloni LP, Goldberg EI, Villa T, Brayton RK, Sangiovanni-Vincentelli AL. Aura II: Combining Negative Thinking and Branch-and-Bound in Unate Covering Problems Ieee Transactions On Very Large Scale Integration Systems. 346-361. DOI: 10.1007/978-0-387-35498-9_31 |
0.551 |
|
1998 |
Goldberg EI, Villa T, Brayton RK, Sangiovanni-Vincentelli AL. Theory and algorithms for face hypercube embedding Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 17: 472-488. DOI: 10.1109/43.703829 |
0.587 |
|
1998 |
Taşıran S, Khatri SP, Yovine S, Brayton RK, Sangiovanni-Vincentelli A. A timed automaton-based method for accurate computation of circuit delay in the presence of cross-talk Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 1522: 149-166. |
0.588 |
|
1997 |
Kam T, Villa T, Brayton RK, Sangiovanni-Vincentelli AL. Theory and algorithms for state minimization of nondeterministic FSM's Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 16: 1311-1322. DOI: 10.1109/43.663820 |
0.581 |
|
1997 |
Villa T, Saldanha A, Brayton RK, Sangiovanni-Vincentelli AL. Symbolic two-level minimization Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 16: 692-708. DOI: 10.1109/43.644031 |
0.554 |
|
1997 |
Villa T, Kam T, Brayton RK, Sangiovanni-Vincentelli AL. Explicit and implicit algorithms for binate covering problems Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 16: 677-691. DOI: 10.1109/43.644030 |
0.591 |
|
1997 |
Kam T, Villa T, Brayton RK, Sangiovanni-Vincentelli AL. Implicit computation of compatible sets for state minimization of ISFSM's Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 16: 657-676. DOI: 10.1109/43.644029 |
0.522 |
|
1996 |
Cheng S, Brayton RK. Synthesizing multi-phase HDL programs Image and Vision Computing. 67-76. DOI: 10.1109/Ivc.1996.496020 |
0.319 |
|
1996 |
Stephan P, Brayton RK, Sangiovanni-Vincentelli AL. Combinational test generation using satisfiability Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 15: 1167-1176. DOI: 10.1109/43.536723 |
0.538 |
|
1996 |
Lam WKC, Brayton RK, Sangiovanni-Vincentelli AL. Valid clock frequencies and their computation in wavepipelined circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 15: 791-807. DOI: 10.1109/43.503946 |
0.558 |
|
1996 |
Jain J, Narayan A, Coelho C, Khatri SP, Sangiovanni-Vincentelli A, Brayton RK, Fujita M. Decomposition techniques for efficient ROBDD construction Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 1166: 419-434. DOI: 10.1007/BFb0031825 |
0.669 |
|
1996 |
Brayton RK, Hachtel GD, Sangiovanni-Vincentelli A, Somenzi F, Aziz A, Cheng ST, Edwards SA, Khatri SP, Kukimoto Y, Pardo A, Qadeer S, Ranjan RK, Sarwary S, Shiple TR, Swamy G, et al. VIS Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 1166: 248-256. DOI: 10.1007/BFb0031812 |
0.426 |
|
1996 |
Hojati R, Isles A, Kirkpatrick D, Brayton RK. Verification using uninterpreted functions and finite instantiations Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 1166: 218-232. DOI: 10.1007/BFb0031810 |
0.739 |
|
1996 |
Brayton RK, Somenzi F, Khatri S, Ranjan RK, Villa T, Hachtel GD, Sangiovanni-Vincentelli A, Aziz A, Cheng ST, Edwards S, Kukimoto Y, Pardo A, Qadeer S, Sarwary S, Shiple TR, et al. VIS: A system for verification and synthesis Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 1102: 428-432. DOI: 10.1007/3-540-61474-5_95 |
0.585 |
|
1996 |
Taşiran S, Alur R, Kurshan RP, Brayton RK. Verifying abstractions of timed systems Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 1119: 546-562. |
0.313 |
|
1996 |
Narayan A, Khatri SP, Jain J, Fujita M, Brayton RK, Sangiovanni-Vincentelli A. Study of composition schemes for mixed apply/compose based construction of ROBDDs Proceedings of the Ieee International Conference On Vlsi Design. 249-252. |
0.531 |
|
1995 |
Cheng S, Brayton RK, York G, Yelick K, Saldanha A. Compiling Verilog into timed finite state machines Image and Vision Computing. 32-39. DOI: 10.1109/Ivc.1995.512465 |
0.35 |
|
1995 |
Lam WK, Saldanha A, Brayton RK, Sangiovanni-Vincentelli AL. Delay Fault Coverage, Test Set Size, and Performance Trade-Offs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 14: 32-44. DOI: 10.1109/43.363125 |
0.503 |
|
1995 |
Lavagno L, Moon CW, Brayton RK, Sangiovanni-Vincentelli AL. An Efficient Heuristic Procedure for Solving the State Assignment Problem for Event-Based Specifications Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 14: 45-60. DOI: 10.1109/43.363124 |
0.564 |
|
1995 |
Aziz A, Balarin F, Brayton RK, DiBenedetto MD, Saldanha A, Sangiovanni-Vincentelli AL. Supervisory control of finite state machines Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 939: 279-292. |
0.495 |
|
1995 |
Aziz A, Singhal V, Balarin F, Brayton RK, Sangiovanni-Vincentelli AL. It usually works: The temporal logic of stochastic systems Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 939: 155-165. |
0.47 |
|
1994 |
Saldanha A, Brayton RK, Sangiovanni-Vincentelli AL. Circuit Structure Relations to Redundancy and Delay Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 13: 875-883. DOI: 10.1109/43.293944 |
0.571 |
|
1994 |
Saldanha A, Villa T, Brayton RK, Sangiovanni-Vincentelli AL. Satisfaction of Input and Output Encoding Constraints Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 13: 589-602. DOI: 10.1109/43.277632 |
0.598 |
|
1994 |
Aziz A, Balarin F, Cheng ST, Hojati R, Kam T, Krishnan SC, Ranjan RK, Shiple TR, Singhal V, Tasiran S, Wang HY, Brayton RK, Sangiovanni-Vincentelli AL. HSIS: a BDD-based environment for formal verification Proceedings - Design Automation Conference. 454-459. |
0.517 |
|
1993 |
Malik S, Singh KJ, Brayton RK, Sangiovanni-Vincentelli A. Performance Optimization of Pipelined Logic Circuits Using Peripheral Retiming and Resynthesis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 12: 568-578. DOI: 10.1109/43.277605 |
0.591 |
|
1993 |
Touati HJ, Brayton RK. Computing the initial states of retimed circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 12: 157-162. DOI: 10.1109/43.184852 |
0.41 |
|
1993 |
Malik AA, Brayton RK, Newton AR, Sangiovanni-Vincentelli AL. Two-Level Minimization of Multivalued Functions with Large Offsets Ieee Transactions On Computers. 42: 1325-1342. DOI: 10.1109/12.247837 |
0.578 |
|
1992 |
Malik S, Lavagno L, Brayton RK, Sangiovanni-Vincentelli A. Symbolic Minimization of Multilevel Logic and the Input Encoding Problem Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 11: 825-843. DOI: 10.1109/43.144847 |
0.572 |
|
1991 |
Malik AA, Brayton RK, Newton AR, Sangiovanni-Vincentelli A. Reduced Offsets for Minimization of Binary-Valued Functions Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 10: 413-426. DOI: 10.1109/43.75625 |
0.553 |
|
1991 |
Malik S, Sentovich EM, Brayton RK, Sangiovanni-Vincentelli A. Retiming and Resynthesis: Optimizing Sequential Networks with Combinational Techniques Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 10: 74-84. DOI: 10.1109/43.62793 |
0.538 |
|
1990 |
Brayton RK, Hachtel GD, Sangiovanni-Vincentelli AL. Multilevel Logic Synthesis Proceedings of the Ieee. 78: 264-300. DOI: 10.1109/5.52213 |
0.454 |
|
1988 |
Bartlett KA, Brayton RK, Hachtel GD, Jacoby RM, Morrison CR, Rudell RL, SangiovannI-Vincentelli A, Wang AR. Multilevel Logic Minimization Using Implicit Don't Cares Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 7: 723-740. DOI: 10.1109/43.3211 |
0.567 |
|
1987 |
Brayton RK, Rudell R, Sangiovanni-Vincentelli A, Wang AR. MIS: A Multiple-Level Logic Optimization System Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 6: 1062-1081. DOI: 10.1109/Tcad.1987.1270347 |
0.561 |
|
1986 |
Micheli GD, Brayton RK, Sangiovanni-Vincentelli A. Correction to “Optimal State Assignment for Finite State Machines” 1 Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 5: 239. DOI: 10.1109/Tcad.1986.1270192 |
0.481 |
|
1985 |
Brayton RK. FACTORING LOGIC FUNCTIONS Ibm Journal of Research and Development. 31: 187-198. DOI: 10.1147/Rd.312.0187 |
0.394 |
|
1985 |
Micheli GD, Brayton RK, Sangiovanni-Vincentelli A. Optimal State Assignment for Finite State Machines Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 4: 269-285. DOI: 10.1109/Tcad.1985.1270123 |
0.577 |
|
1981 |
Brayton RK, Hachtel GD, Sangiovanni-Vincentelli AL. A Survey of Optimization Techniques for Integrated-Circuit Design Proceedings of the Ieee. 69: 1334-1362. DOI: 10.1109/PROC.1981.12170 |
0.486 |
|
1980 |
Brayton RK, Director SW, Hachtel GD. Yield Maximization and Worst-Case Design with Arbitrary Statistical Distributions Ieee Transactions On Circuits and Systems. 27: 756-764. DOI: 10.1109/Tcs.1980.1084889 |
0.386 |
|
1980 |
Brayton RK, Tong CH. Constructive Stability and Asymptotic Stability of Dynamical Systems Ieee Transactions On Circuits and Systems. 27: 1121-1130. DOI: 10.1109/Tcs.1980.1084749 |
0.331 |
|
1979 |
Brayton RK, Hachtel GD, Director SW, Vidigal LM. A New Algorithm for Statistical Circuit Design Based on Quasi-Newton Methods and Function Splitting Ieee Transactions On Circuits and Systems. 26: 784-794. DOI: 10.1109/Tcs.1979.1084701 |
0.423 |
|
1979 |
Brayton RK, Cullum J. An algorithm for minimizing a differentiable function subject to box constraints and errors Journal of Optimization Theory and Applications. 29: 521-558. DOI: 10.1007/Bf00934451 |
0.365 |
|
1979 |
Cullum J, Brayton RK. Some remarks on the symmetric rank-one update Journal of Optimization Theory and Applications. 29: 493-519. DOI: 10.1007/Bf00934450 |
0.37 |
|
1977 |
Brayton RK, Scott TR, Hoffman AJ. A Theorem on Inverses of Convex Sets of Real Matrices with Application to the Worst Case DC Problem Ieee Transactions On Circuits and Systems. 24: 409-415. DOI: 10.1109/Tcs.1977.1084365 |
0.325 |
|
1975 |
Brayton RK, Director SW. Computation of Delay Time Sensitivities for Use in Time Domain Optimization Ieee Transactions On Circuits and Systems. 22: 910-920. DOI: 10.1109/Tcs.1975.1083997 |
0.364 |
|
1971 |
Hachtel GD, Brayton RK, Gustavson FG. The Sparse Tableau Approach to Network Analysis and Design Ieee Transactions On Circuit Theory. 18: 101-113. DOI: 10.1109/Tct.1971.1083223 |
0.373 |
|
1970 |
Brayton RK, Gustavson FG, Willoughby RA. Some results on sparse matrices Mathematics of Computation. 24: 937-954. DOI: 10.1090/S0025-5718-1970-0275643-8 |
0.303 |
|
1964 |
Brayton RK. Stability criteria for large networks Ibm Journal of Research and Development. 8: 466-470. DOI: 10.1147/Rd.84.0466 |
0.311 |
|
1964 |
Brayton RK. On the Effect of Component Tolerances in the Balanced-Pair Tunnel-Diode Circuit Ieee Transactions On Circuit Theory. 11: 351-356. DOI: 10.1109/Tct.1964.1082313 |
0.313 |
|
1964 |
Brayton RK, Miranker WL. A stability theory for nonlinear mixed initial boundary value problems Archive For Rational Mechanics and Analysis. 17: 358-376. DOI: 10.1007/Bf00250472 |
0.3 |
|
1963 |
Brayton R, Willoughby R. An Analysis of the Effect of Component Tolerances on the Amplification of the Balanced-Pair Tunnel-Diode Circuit Ieee Transactions On Electronic Computers. 12: 269-274. DOI: 10.1109/Pgec.1963.263539 |
0.366 |
|
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