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Ajay N. Bhoj, Ph.D. - Publications

Affiliations: 
2013 Electrical Engineering Princeton University, Princeton, NJ 
Area:
Biological & Biomedical,Computing & Networking,Energy & Environment,High-Performance Computing,Integrated Electronic Systems,Nanotechnologies,Quantum Information,Security
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14 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2016 Chaudhuri S, Bhoj AN, Bhattacharya D, Jha NK. Fast FinFET Device Simulation under Process-Voltage Variations Using an Assisted Speed-Up Mechanism Proceedings of the Ieee International Conference On Vlsi Design. 2016: 300-305. DOI: 10.1109/VLSID.2016.34  0.652
2015 Bhattacharya D, Bhoj AN, Jha NK. Design of efficient content addressable memories in high-performance FinFET technology Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 23: 963-967. DOI: 10.1109/Tvlsi.2014.2319192  0.568
2015 Joshi RV, Kim K, Kanj R, Bhoj AN, Ziegler MM, Oldiges P, Kerber P, Wong R, Hook T, Saroop S, Radens C, Yeh CC. Super fast physics-based methodology for accurate memory yield prediction Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 23: 534-543. DOI: 10.1109/Tvlsi.2014.2313815  0.446
2014 Bhoj AN, Jha NK. Parasitics-aware design of symmetric and asymmetric gate-workfunction finFET SRAMs Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 22: 548-561. DOI: 10.1109/Tvlsi.2013.2252031  0.488
2013 Bhoj AN, Jha NK. Design of logic gates and flip-flops in high-performance finFET technology Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 21: 1975-1988. DOI: 10.1109/Tvlsi.2012.2227850  0.557
2013 Bhoj AN, Joshi RV, Jha NK. 3-D-TCAD-based parasitic capacitance extraction for emerging multigate devices and circuits Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 21: 2094-2105. DOI: 10.1109/Tvlsi.2012.2227848  0.551
2013 Bhoj AN, Joshi RV, Jha NK. Efficient methodologies for 3-D TCAD modeling of emerging devices and circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 32: 47-58. DOI: 10.1109/TCAD.2012.2210421  0.377
2012 Bhoj AN, Simsir MO, Jha NK. Fault models for logic circuits in the multigate era Ieee Transactions On Nanotechnology. 11: 182-193. DOI: 10.1109/Tnano.2011.2169807  0.585
2012 Bhoj AN, Joshi RV. Transport-analysis-based 3-D TCAD capacitance extraction for sub-32-nm SRAM structures Ieee Electron Device Letters. 33: 158-160. DOI: 10.1109/LED.2011.2175359  0.305
2011 Bhoj AN, Jha NK. Design of ultra-low-leakage logic gates and flip-flops in high-performance FinFET technology Proceedings of the 12th International Symposium On Quality Electronic Design, Isqed 2011. 695-702. DOI: 10.1109/ISQED.2011.5770805  0.397
2010 Bhoj AN, Jha NK. Gated-diode FinFET DRAMs: Device and circuit design-considerations Acm Journal On Emerging Technologies in Computing Systems. 6. DOI: 10.1145/1877745.1877746  0.579
2010 Simsir MO, Bhoj A, Jha NK. Fault modeling for FinFET circuits Proceedings of the 2010 Ieee/Acm International Symposium On Nanoscale Architectures, Nanoarch 2010. 41-46. DOI: 10.1109/NANOARCH.2010.5510927  0.604
2010 Mishra P, Bhoj AN, Jha NK. Die-level leakage power analysis of FinFET circuits considering process variations Proceedings of the 11th International Symposium On Quality Electronic Design, Isqed 2010. 347-355. DOI: 10.1109/ISQED.2010.5450554  0.446
2009 Bhoj AN, Jha NK. Pragmatic design of gated-diode finFET DRAMs Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 390-397. DOI: 10.1109/ICCD.2009.5413127  0.503
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