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Kaustav Banerjee - Publications

Affiliations: 
Electrical & Computer Engineering University of California, Santa Barbara, Santa Barbara, CA, United States 
Area:
Computer Engineering/ Electronics & Photonics
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125 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2023 Cao W, Bu H, Vinet M, Cao M, Takagi S, Hwang S, Ghani T, Banerjee K. The future transistors. Nature. 620: 501-515. PMID 37587295 DOI: 10.1038/s41586-023-06145-x  0.328
2020 Cao W, Banerjee K. Author Correction: Is negative capacitance FET a steep-slope logic switch? Nature Communications. 11: 1094. PMID 32094343 DOI: 10.1038/S41467-020-14795-Y  0.311
2020 Cao W, Banerjee K. Is negative capacitance FET a steep-slope logic switch? Nature Communications. 11: 196. PMID 31924760 DOI: 10.1038/S41467-019-13797-9  0.421
2020 Pal A, Cao W, Banerjee K. A Compact Current-Voltage Model for 2-D-Semiconductor-Based Lateral Homo-/Hetero-Junction Tunnel-FETs Ieee Transactions On Electron Devices. 1-9. DOI: 10.1109/Ted.2020.3011350  0.352
2020 Cao W, Huang M, Yeh C, Parto K, Banerjee K. Impact of Transport Anisotropy on the Performance of van der Waals Materials-Based Electron Devices Ieee Transactions On Electron Devices. 67: 1310-1316. DOI: 10.1109/Ted.2020.2970394  0.41
2020 Xu C, Kolluri SK, Endo K, Banerjee K. Correction to “Analytical Thermal Model for Self-Heating in Advanced FinFET Devices With Implications for Design and Reliability” Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 39: 277-277. DOI: 10.1109/Tcad.2019.2944583  0.503
2019 Jiang J, Parto K, Cao W, Banerjee K. Ultimate Monolithic-3D Integration With 2D Materials: Rationale, Prospects, and Challenges Ieee Journal of the Electron Devices Society. 7: 878-887. DOI: 10.1109/Jeds.2019.2925150  0.355
2018 Cao W, Jiang J, Xie X, Pal A, Chu JH, Kang J, Banerjee K. 2-D Layered Materials for Next-Generation Electronics: Opportunities and Challenges Ieee Transactions On Electron Devices. 65: 4109-4121. DOI: 10.1109/Ted.2018.2867441  0.368
2017 Hu Y, Brus V, Cao W, Liao K, Phan H, Wang M, Banerjee K, Bazan GC, Nguyen TQ. Understanding the Device Physics in Polymer-Based Ionic-Organic Ratchets. Advanced Materials (Deerfield Beach, Fla.). PMID 28169462 DOI: 10.1002/Adma.201606464  0.411
2016 Jiang J, Kang J, Cao W, Xie X, Zhang H, Chu JH, Liu W, Banerjee K. Intercalation Doped Multilayer-Graphene-Nanoribbons for Next-Generation Interconnects. Nano Letters. PMID 28005374 DOI: 10.1021/Acs.Nanolett.6B04516  0.396
2016 Lei S, Wang X, Li B, Kang J, He Y, George A, Ge L, Gong Y, Dong P, Jin Z, Brunetto G, Chen W, Lin ZT, Baines R, Galvão DS, ... ... Banerjee K, et al. Surface functionalization of two-dimensional metal chalcogenides by Lewis acid-base chemistry. Nature Nanotechnology. PMID 26828848 DOI: 10.1038/Nnano.2015.323  0.364
2016 Cao W, Liu W, Kang J, Banerjee K. An Ultra-Short Channel Monolayer MoS2 FET Defined By the Curvature of a Thin Nanowire Ieee Electron Device Letters. 37: 1497-1500. DOI: 10.1109/Led.2016.2614663  0.394
2016 Liu W, Kang J, Banerjee K. Characterization of FeCl3 Intercalation Doped CVD Few-Layer Graphene Ieee Electron Device Letters. 37: 1246-1249. DOI: 10.1109/Led.2016.2597099  0.333
2016 Cao W, Jiang J, Kang J, Sarkar D, Liu W, Banerjee K. Designing band-to-band tunneling field-effect transistors with 2D semiconductors for next-generation low-power VLSI Technical Digest - International Electron Devices Meeting, Iedm. 2016: 12.3.1-12.3.4. DOI: 10.1109/IEDM.2015.7409682  0.304
2016 Simanullang M, Wisna GBM, Usami K, Cao W, Kawano Y, Banerjee K, Oda S. Undoped and catalyst-free germanium nanowires for high-performance p-type enhancement-mode field-effect transistors Journal of Materials Chemistry C. 4: 5102-5108. DOI: 10.1039/C6Tc00352D  0.351
2015 Allain A, Kang J, Banerjee K, Kis A. Electrical contacts to two-dimensional semiconductors. Nature Materials. 14: 1195-205. PMID 26585088 DOI: 10.1038/Nmat4452  0.407
2015 Sarkar D, Xie X, Liu W, Cao W, Kang J, Gong Y, Kraemer S, Ajayan PM, Banerjee K. A subthermionic tunnel field-effect transistor with an atomically thin channel. Nature. 526: 91-5. PMID 26432247 DOI: 10.1038/Nature15387  0.425
2015 Liu W, Sarkar D, Kang J, Cao W, Banerjee K. Impact of Contact on the Operation and Performance of Back-Gated Monolayer MoS2 Field-Effect-Transistors. Acs Nano. PMID 26039221 DOI: 10.1021/Nn506512J  0.402
2015 Sarkar D, Xie X, Kang J, Zhang H, Liu W, Navarrete J, Moskovits M, Banerjee K. Functionalization of transition metal dichalcogenides with metallic nanoparticles: implications for doping and gas-sensing. Nano Letters. 15: 2852-62. PMID 25723363 DOI: 10.1021/Nl504454U  0.345
2015 Tadi KK, Narayanan TN, Arepalli S, Banerjee K, Viswanathan S, Liepmann D, Ajayan PM, Renugopalakrishnan V. Engineered 2D nanomaterials–protein interfaces for efficient sensors Journal of Materials Research. 1-10. DOI: 10.1557/Jmr.2015.349  0.358
2015 Cao W, Kang J, Sarkar D, Liu W, Banerjee K. 2D Semiconductor FETs - Projections and Design for Sub-10 nm VLSI Ieee Transactions On Electron Devices. 62: 3459-3469. DOI: 10.1109/Ted.2015.2443039  0.412
2015 Li X, Kang J, Xie X, Liu W, Sarkar D, Mao J, Banerjee K. Graphene inductors for high-frequency applications - Design, fabrication, characterization, and study of skin effect Technical Digest - International Electron Devices Meeting, Iedm. 2015: 5.4.1-5.4.4. DOI: 10.1109/IEDM.2014.7046989  0.301
2014 Jena D, Banerjee K, Xing GH. 2D crystal semiconductors: Intimate contacts. Nature Materials. 13: 1076-8. PMID 25410976 DOI: 10.1038/Nmat4121  0.373
2014 Xie X, Sarkar D, Liu W, Kang J, Marinov O, Deen MJ, Banerjee K. Low-frequency noise in bilayer MoS(2) transistor. Acs Nano. 8: 5633-40. PMID 24708223 DOI: 10.1021/Nn4066473  0.402
2014 Sarkar D, Liu W, Xie X, Anselmo AC, Mitragotri S, Banerjee K. MoS₂ field-effect transistor for next-generation label-free biosensors. Acs Nano. 8: 3992-4003. PMID 24588742 DOI: 10.1021/Nn5009148  0.391
2014 Kang J, Cao W, Xie X, Sarkar D, Liu W, Banerjee K. Graphene and beyond-graphene 2D crystals for next-generation green electronics Proceedings of Spie - the International Society For Optical Engineering. 9083. DOI: 10.1117/12.2051198  0.349
2014 Khatami Y, Li H, Liu W, Banerjee K. On the electrostatics of bernal-stacked few-layer graphene on surface-passivated semiconductors Ieee Transactions On Nanotechnology. 13: 94-100. DOI: 10.1109/Tnano.2013.2293355  0.766
2014 Cao W, Kang J, Liu W, Banerjee K. A compact current-voltage model for 2D semiconductor based field-effect transistors considering interface traps, mobility degradation, and inefficient doping effect Ieee Transactions On Electron Devices. 61: 4282-4290. DOI: 10.1109/Ted.2014.2365028  0.424
2014 Cao W, Kang J, Bertolazzi S, Kis A, Banerjee K. Can 2D-nanocrystals extend the lifetime of floating-gate transistor based nonvolatile memory? Ieee Transactions On Electron Devices. 61: 3456-3464. DOI: 10.1109/Ted.2014.2350483  0.387
2014 Li H, Russ CC, Liu W, Johnsson D, Gossner H, Banerjee K. On the electrostatic discharge robustness of graphene Ieee Transactions On Electron Devices. 61: 1920-1928. DOI: 10.1109/Ted.2014.2315235  0.367
2014 Kang J, Liu W, Sarkar D, Jena D, Banerjee K. Computational study of metal contacts to monolayer transition-metal dichalcogenide semiconductors Physical Review X. 4. DOI: 10.1103/Physrevx.4.031005  0.396
2014 Cao W, Sarkar D, Khatami Y, Kang J, Banerjee K. Subthreshold-swing physics of tunnel field-effect transistors Aip Advances. 4. DOI: 10.1063/1.4881979  0.777
2014 Kang J, Liu W, Banerjee K. High-performance MoS2 transistors with low-resistance molybdenum contacts Applied Physics Letters. 104. DOI: 10.1063/1.4866340  0.395
2014 Liu W, Kraemer S, Sarkar D, Li H, Ajayan PM, Banerjee K. Controllable and rapid synthesis of high-quality and large-area bernal stacked bilayer graphene using chemical vapor deposition Chemistry of Materials. 26: 907-915. DOI: 10.1021/Cm4021854  0.35
2013 Liu W, Kang J, Sarkar D, Khatami Y, Jena D, Banerjee K. Role of metal contacts in designing high-performance monolayer n-type WSe2 field effect transistors. Nano Letters. 13: 1983-90. PMID 23527483 DOI: 10.1021/Nl304777E  0.791
2013 Khatami Y, Liu W, Kang J, Banerjee K. Prospects of graphene electrodes in photovoltaics Proceedings of Spie - the International Society For Optical Engineering. 8824. DOI: 10.1117/12.2026581  0.757
2013 Li H, Liu W, Cassell AM, Kreupl F, Banerjee K. Low-resistivity long-length horizontal carbon nanotube bundles for interconnect applications - Part i: Process development Ieee Transactions On Electron Devices. 60: 2862-2869. DOI: 10.1109/Ted.2013.2275259  0.416
2013 Li H, Liu W, Cassell AM, Kreupl F, Banerjee K. Low-resistivity long-length horizontal carbon nanotube bundles for interconnect applications - Part ii: Characterization Ieee Transactions On Electron Devices. 60: 2870-2876. DOI: 10.1109/Ted.2013.2275258  0.349
2013 Xu C, Banerjee K. Physical modeling of the capacitance and capacitive coupling noise of through-oxide vias in FDSOI-based ultra-high density 3-D ICs Ieee Transactions On Electron Devices. 60: 123-131. DOI: 10.1109/Ted.2012.2227966  0.53
2013 Xu C, Kolluri SK, Endo K, Banerjee K. Analytical thermal model for self-heating in advanced FinFET devices with implications for design and reliability Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 32: 1045-1058. DOI: 10.1109/Tcad.2013.2248194  0.549
2013 Liu W, Kang J, Cao W, Sarkar D, Khatami Y, Jena D, Banerjee K. High-performance few-layer-MoS2 field-effect-transistor with record low contact-resistance Technical Digest - International Electron Devices Meeting, Iedm. 19.4.1-19.4.4. DOI: 10.1109/IEDM.2013.6724660  0.786
2013 Zhao P, Hwang WS, Kim ES, Feenstra R, Gu G, Kang J, Banerjee K, Seabaugh A, Xing G, Jena D. Novel logic devices based on 2D crystal semiconductors: Opportunities and challenges Technical Digest - International Electron Devices Meeting, Iedm. 19.1.1-19.1.4. DOI: 10.1109/IEDM.2013.6724657  0.312
2013 Cao W, Kang J, Liu W, Khatami Y, Sarkar D, Banerjee K. 2D electronics: Graphene and beyond European Solid-State Device Research Conference. 37-44. DOI: 10.1109/ESSDERC.2013.6818814  0.752
2013 Kang J, Cao W, Sarkar D, Khatami Y, Liu W, Banerjee K. 2-Dimensional tunnel devices and circuits on graphene: Opportunities and challenges 2013 3rd Berkeley Symposium On Energy Efficient Electronic Systems, E3s 2013 - Proceedings. DOI: 10.1109/E3S.2013.6705879  0.789
2013 Kang J, Sarkar D, Khatami Y, Banerjee K. Proposal for all-graphene monolithic logic circuits Applied Physics Letters. 103. DOI: 10.1063/1.4818462  0.809
2013 Sarkar D, Gossner H, Hansch W, Banerjee K. Impact-ionization field-effect-transistor based biosensors for ultra-sensitive detection of biomolecules Applied Physics Letters. 102. DOI: 10.1063/1.4804577  0.333
2013 Khatami Y, Kang J, Banerjee K. Graphene nanoribbon based negative resistance device for ultra-low voltage digital logic applications Applied Physics Letters. 102. DOI: 10.1063/1.4788684  0.806
2013 Sarkar D, Gossner H, Hansch W, Banerjee K. Tunnel-field-effect-transistor based gas-sensor: Introducing gas detection with a quantum-mechanical transducer Applied Physics Letters. 102. DOI: 10.1063/1.4775358  0.347
2012 Xu C, Suaya R, Banerjee K. Some clarifications on "compact modeling and analysis of through-si-via induced electrical noise coupling in three-dimensional ICs" Ieee Transactions On Electron Devices. 59: 2861-2862. DOI: 10.1109/Ted.2012.2209431  0.457
2012 Khatami Y, Li H, Xu C, Banerjee K. Metal-to-multilayer-graphene contact part II: Analysis of contact resistance Ieee Transactions On Electron Devices. 59: 2453-2460. DOI: 10.1109/Ted.2012.2205257  0.786
2012 Khatami Y, Li H, Xu C, Banerjee K. Metal-to-multilayer-graphene contact part I: Contact resistance modeling Ieee Transactions On Electron Devices. 59: 2444-2452. DOI: 10.1109/Ted.2012.2205256  0.799
2012 Xu C, Srivastava N, Suaya R, Banerjee K. Fast high-frequency impedance extraction of horizontal interconnects and inductors in 3-D ICs with multiple substrates Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 1698-1710. DOI: 10.1109/Tcad.2012.2203598  0.659
2012 Burkhardt M, Liu W, Shuttle CG, Banerjee K, Chabinyc ML. Top illuminated inverted organic ultraviolet photosensors with single layer graphene electrodes Applied Physics Letters. 101. DOI: 10.1063/1.4733299  0.342
2012 Sarkar D, Banerjee K. Proposal for tunnel-field-effect-transistor as ultra-sensitive and label-free biosensors Applied Physics Letters. 100. DOI: 10.1063/1.3698093  0.324
2011 Xu C, Suaya R, Banerjee K. Compact modeling and analysis of through-Si-Via-induced electrical noise coupling in three-dimensional ICs Ieee Transactions On Electron Devices. 58: 4024-4034. DOI: 10.1109/Ted.2011.2166156  0.501
2011 Xu C, Kourkoulos V, Suaya R, Banerjee K. A fully analytical model for the series impedance of through-silicon vias with consideration of substrate effects and coupling with horizontal interconnects Ieee Transactions On Electron Devices. 58: 3529-3540. DOI: 10.1109/Ted.2011.2162846  0.502
2011 Li H, Srivastava N, Mao JF, Yin WY, Banerjee K. Carbon nanotube vias: Does ballistic electron-phonon transport imply improved performance and reliability? Ieee Transactions On Electron Devices. 58: 2689-2701. DOI: 10.1109/Ted.2011.2157825  0.606
2011 Rasouli SH, Endo K, Chen JF, Singh N, Banerjee K. Grain-orientation induced quantum confinement variation in FinFETs and multi-gate ultra-thin body CMOS devices and implications for digital design Ieee Transactions On Electron Devices. 58: 2282-2292. DOI: 10.1109/Ted.2011.2151196  0.749
2011 Sarkar D, Xu C, Li H, Banerjee K. High-frequency behavior of graphene-based interconnect-sPart II: Impedance analysis and implications for inductor design Ieee Transactions On Electron Devices. 58: 853-859. DOI: 10.1109/Ted.2010.2102035  0.532
2011 Sarkar D, Xu C, Li H, Banerjee K. High-frequency behavior of graphene-based interconnects-Part I: Impedance modeling Ieee Transactions On Electron Devices. 58: 843-852. DOI: 10.1109/Ted.2010.2102031  0.532
2011 Rasouli SH, Xu C, Singh N, Banerjee K. A physical model for work-function variation in ultra-short channel metal-gate mosfets Ieee Electron Device Letters. 32: 1507-1509. DOI: 10.1109/Led.2011.2166531  0.754
2011 Li X, Chen Z, Shen N, Sarkar D, Singh N, Banerjee K, Lo GQ, Kwong DL. Vertically stacked and independently controlled twin-gate MOSFETs on a single si nanowire Ieee Electron Device Letters. 32: 1492-1494. DOI: 10.1109/Led.2011.2165693  0.444
2011 Gandhi R, Chen Z, Singh N, Banerjee K, Lee S. CMOS-Compatible vertical-silicon-nanowire gate-all-around P-Type tunneling FETs with ≤ 5-mV/decade subthreshold swing Ieee Electron Device Letters. 32: 1504-1506. DOI: 10.1109/Led.2011.2165331  0.422
2011 Gandhi R, Chen Z, Singh N, Banerjee K, Lee S. Vertical Si-Nanowire n-type tunneling FETs with low subthreshold swing ≤50 mV/decade) at room temperature Ieee Electron Device Letters. 32: 437-439. DOI: 10.1109/Led.2011.2106757  0.383
2011 Dadgour HF, Hussain MM, Cassell A, Singh N, Banerjee K. Impact of scaling on the performance and reliability degradation of metal-contacts in NEMS devices Ieee International Reliability Physics Symposium Proceedings. 3D.3.1-3D.3.10. DOI: 10.1109/IRPS.2011.5784489  0.769
2011 Liu W, Li H, Xu C, Khatami Y, Banerjee K. Synthesis of high-quality monolayer and bilayer graphene on copper using chemical vapor deposition Carbon. 49: 4122-4130. DOI: 10.1016/J.Carbon.2011.05.047  0.771
2010 Dadgour HF, Hussain MM, Banerjee K. A new paradigm in the design of energy-efficient digital circuits using laterally-actuated double-gate NEMS Proceedings of the International Symposium On Low Power Electronics and Design. 7-12. DOI: 10.1145/1840845.1840848  0.758
2010 Dadgour HF, Hussain MM, Smith C, Banerjee K. Design and analysis of compact ultra energy-efficient logic gates using laterally-actuated double-electrode NEMS Proceedings - Design Automation Conference. 893-896. DOI: 10.1145/1837274.1837498  0.748
2010 Dadgour HF, Banerjee K. A Novel Variation-Tolerant Keeper Architecture for High-Performance Low-Power Wide Fan-In Dynamic or Gates Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 18: 1567-1577. DOI: 10.1109/Tvlsi.2009.2025591  0.789
2010 Xu C, Li H, Suaya R, Banerjee K. Compact AC modeling and performance analysis of through-silicon vias in 3-D ICs Ieee Transactions On Electron Devices. 57: 3405-3417. DOI: 10.1109/Ted.2010.2076382  0.545
2010 Rasouli SH, Dadgour HF, Endo K, Koike H, Banerjee K. Design optimization of FinFET domino logic considering the width quantization property Ieee Transactions On Electron Devices. 57: 2934-2943. DOI: 10.1109/Ted.2010.2076374  0.804
2010 Dadgour HF, Endo K, De VK, Banerjee K. Grain-orientation induced work function variation in nanoscale metal-gate transistors - Part II: Implications for process, device, and circuit design Ieee Transactions On Electron Devices. 57: 2515-2525. DOI: 10.1109/Ted.2010.2063270  0.814
2010 Dadgour HF, Endo K, De VK, Banerjee K. Grain-orientation induced work function variation in nanoscale metal-gate transistors - Part I: Modeling, analysis, and experimental validation Ieee Transactions On Electron Devices. 57: 2504-2514. DOI: 10.1109/Ted.2010.2063191  0.802
2010 Srivastava N, Xu C, Suaya R, Banerjee K. Corrections to “Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multilayer Conductive Substrate” [Jul 09 1047-1060 Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 29: 849-849. DOI: 10.1109/Tcad.2010.2047753  0.618
2010 Jiang L, Xu C, Rubin BJ, Weger AJ, Deutsch A, Smith H, Caron A, Banerjee K. A thermal simulation process based on electrical modeling for complex interconnect, packaging, and 3DI structures Ieee Transactions On Advanced Packaging. 33: 777-786. DOI: 10.1109/Tadvp.2010.2090348  0.499
2010 Banerjee K, Li H, Xu C, Khatami Y, Dadgour HF, Sarkar D, Liu W. Prospects of carbon nanomaterials for next-generation green electronics 2010 10th Ieee Conference On Nanotechnology, Nano 2010. 56-61. DOI: 10.1109/NANO.2010.5698053  0.737
2010 Li H, Xu C, Banerjee K. Carbon nanomaterials: The ideal interconnect technology for next-generation ICs Ieee Design and Test of Computers. 27: 20-31. DOI: 10.1109/Mdt.2010.55  0.513
2010 Sarkar D, Singh N, Banerjee K. A novel enhanced electric-field impact-ionization MOS transistor Ieee Electron Device Letters. 31: 1175-1177. DOI: 10.1109/Led.2010.2066541  0.433
2010 Rasouli SH, Banerjee K. Effect of grain orientation on NBTI variation and recovery in emerging metal-gate devices Ieee Electron Device Letters. 31: 794-796. DOI: 10.1109/Led.2010.2051403  0.74
2010 Dadgour HF, Banerjee K. A built-in aging detection and compensation technique for improving reliability of nanoscale CMOS designs Ieee International Reliability Physics Symposium Proceedings. 822-825. DOI: 10.1109/IRPS.2010.5488727  0.736
2010 Rasouli SH, Endo K, Banerjee K. Work-function variation induced fluctuation in bias-temperature-instability characteristics of emerging metal-gate devices and implications for digital design Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 714-720. DOI: 10.1109/ICCAD.2010.5654260  0.735
2010 Khatami Y, Krall M, Li H, Xu C, Banerjee K. Graphene based heterostructure tunnel-FETs for low-voltage/high-performance ICs Device Research Conference - Conference Digest, Drc. 65-66. DOI: 10.1109/DRC.2010.5551939  0.755
2010 Sarkar D, Krall M, Banerjee K. Electron-hole duality during band-to-band tunneling process in graphene-nanoribbon tunnel-field-effect-transistors Applied Physics Letters. 97. DOI: 10.1063/1.3528338  0.35
2010 Dadgour H, Banerjee K. Aging-resilient design of pipelined architectures using novel detection and correction circuits Proceedings -Design, Automation and Test in Europe, Date. 244-249.  0.767
2009 Li H, Xu C, Srivastava N, Banerjee K. Carbon Nanomaterials for Next-Generation Interconnects and Passives: Physics, Status, and Prospects Ieee Transactions On Electron Devices. 56: 1799-1821. DOI: 10.7567/Ssdm.2009.D-8-1  0.709
2009 Srivastava N, Li H, Kreupl F, Banerjee K. On the applicability of single-walled carbon nanotubes as VLSI interconnects Ieee Transactions On Nanotechnology. 8: 542-559. DOI: 10.1109/Tnano.2009.2013945  0.643
2009 Khatami Y, Banerjee K. Steep subthreshold slope n- and p-type Tunnel-FET devices for low-power and energy-efficient digital circuits Ieee Transactions On Electron Devices. 56: 2752-2761. DOI: 10.1109/Ted.2009.2030831  0.799
2009 Li H, Banerjee K. High-frequency analysis of Carbon Nanotube interconnects and implications for on-chip inductor design Ieee Transactions On Electron Devices. 56: 2202-2214. DOI: 10.1109/Ted.2009.2028395  0.356
2009 Xu C, Li H, Banerjee K. Modeling, analysis, and design of graphene nano-ribbon interconnects Ieee Transactions On Electron Devices. 56: 1567-1578. DOI: 10.1109/Ted.2009.2024254  0.559
2009 Srivastava N, Suaya R, Banerjee K. Analytical expressions for high-frequency VLSI interconnect impedance extraction in the presence of a multilayer conductive substrate Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 28: 1047-1060. DOI: 10.1109/Tcad.2009.2017432  0.599
2009 Khatami Y, Banerjee K. Scaling analysis of graphene nanoribbon tunnel-FETs Device Research Conference - Conference Digest, Drc. 197-198. DOI: 10.1109/DRC.2009.5354949  0.764
2009 Dadgour HF, Banerjee K. Hybrid NEMS-CMOS integrated circuits: A novel strategy for energy-efficient designs Iet Computers and Digital Techniques. 3: 593-608. DOI: 10.1049/Iet-Cdt.2008.0148  0.797
2009 Rasouli SH, Endo K, Banerjee K. Variability analysis of FinFET-based devices and circuits considering electrical confinement and width quantization Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 505-512.  0.748
2009 Xu C, Jiang L, Kolluri SK, Rubin BJ, Deutsch A, Smith H, Banerjee K. Fast 3-D thermal analysis of complex interconnect structures using electrical modeling and simulation methodologies Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 658-665.  0.433
2008 Lin S, Banerjee K. A Design-Specific and Thermally-Aware Methodology for Trading-Off Power and Performance in Leakage-Dominant CMOS Technologies Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 16: 1488-1498. DOI: 10.1109/Tvlsi.2008.2001060  0.563
2008 Li H, Yin W, Banerjee K, Mao J. Circuit Modeling and Performance Analysis of Multi-Walled Carbon Nanotube Interconnects Ieee Transactions On Electron Devices. 55: 1328-1337. DOI: 10.1109/Ted.2008.922855  0.38
2008 Lin S, Banerjee K. Cool Chips: Opportunities and Implications for Power and Thermal Management Ieee Transactions On Electron Devices. 55: 245-255. DOI: 10.1109/Ted.2007.911763  0.574
2008 Kshirsagar C, Li H, Kopley TE, Banerjee K. Accurate Intrinsic Gate Capacitance Model for Carbon Nanotube-Array Based FETs Considering Screening Effect Ieee Electron Device Letters. 29: 1408-1411. DOI: 10.1109/Led.2008.2007598  0.364
2008 Dadgour H, De V, Banerjee K. Statistical modeling of metal-gate work-function variability in emerging device technologies and implications for circuit design Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 270-277. DOI: 10.1109/ICCAD.2008.4681585  0.805
2007 Lin S, Chrysler G, Mahajan R, De VK, Banerjee K. A Self-Consistent Substrate Thermal Profile Estimation Technique for Nanoscale ICs—Part I: Electrothermal Couplings and Full-Chip Package Thermal Model Ieee Transactions On Electron Devices. 54: 3342-3350. DOI: 10.1109/Ted.2007.909039  0.545
2007 Lin S, Chrysler G, Mahajan R, De VK, Banerjee K. A Self-Consistent Substrate Thermal Profile Estimation Technique for Nanoscale ICs—Part II: Implementation and Implications for Power Estimation and Thermal Management Ieee Transactions On Electron Devices. 54: 3351-3360. DOI: 10.1109/Ted.2007.909038  0.552
2007 Dadgour HF, Lin SC, Banerjee K. A statistical framework for estimation of full-chip leakage-power distribution under parameter variations Ieee Transactions On Electron Devices. 54: 2930-2945. DOI: 10.1109/Ted.2007.906960  0.79
2007 Mysore S, Agrawal B, Srivastava N, Lin S, Banerjee K, Sherwood T. 3D Integration for Introspection Ieee Micro. 27: 77-83. DOI: 10.1109/Mm.2007.1  0.562
2006 Dadgour HF, Joshi RV, Banerjee K. A novel variation-aware low-power keeper architecture for wide fan-in dynamic gates Proceedings - Design Automation Conference. 977-982. DOI: 10.1145/1146909.1147156  0.778
2005 Im S, Srivastava N, Banerjee K, Goodson KE. Scaling analysis of multilevel interconnect temperatures for high-performance ICs Ieee Transactions On Electron Devices. 52: 2710-2719. DOI: 10.1109/Ted.2005.859612  0.359
2005 Mui ML, Banerjee K, Mehrotra A. Supply and power optimization in leakage-dominant technologies Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 24: 1362-1371. DOI: 10.1109/Tcad.2005.852039  0.321
2005 Ajami AH, Banerjee K, Pedram M. Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 24: 849-860. DOI: 10.1109/Tcad.2005.847944  0.354
2005 Chatterjee A, Schrimpf RD, Pendharkar S, Banerjee K. Mechanisms leading to erratic snapback behavior in bipolar junction transistors with base emitter shorted Journal of Applied Physics. 97. DOI: 10.1063/1.1874294  0.324
2005 Ajami AH, Banerjee K, Pedram M. Scaling analysis of on-chip power grid voltage variations in nanometer scale ULSI Analog Integrated Circuits and Signal Processing. 42: 277-290. DOI: 10.1007/S10470-005-6761-X  0.371
2004 Mui ML, Banerjee K, Mehrotra A. A global interconnect optimization scheme for nanometer scale VLSI with implications for latency, bandwidth, and power dissipation Ieee Transactions On Electron Devices. 51: 195-203. DOI: 10.1109/Ted.2003.820651  0.312
2004 Koukab A, Banerjee K, Declercq M. Modeling Techniques and Verification Methodologies for Substrate Coupling Effects in Mixed-Signal System-on-Chip Designs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 23: 823-836. DOI: 10.1109/Tcad.2004.828117  0.333
2004 Srivastava N, Banerjee K. Interconnect challenges for nanoscale electronic circuits Jom. 56: 30-31. DOI: 10.1007/S11837-004-0285-1  0.629
2002 Oh K, Duvvury C, Banerjee K, Dutton RW. Analysis of nonuniform ESD current distribution in deep submicron NMOS transistors Ieee Transactions On Electron Devices. 49: 2171-2182. DOI: 10.1109/Ted.2002.805049  0.428
2002 Banerjee K, Mehrotra A. A power-optimal repeater insertion methodology for global interconnects in nanometer designs Ieee Transactions On Electron Devices. 49: 2001-2007. DOI: 10.1109/Ted.2002.804706  0.306
2002 Oh K, Duvvury C, Banerjee K, Dutton RW. Impact of gate-to-contact spacing on ESD performance of salicided deep submicron NMOS transistors Ieee Transactions On Electron Devices. 49: 2183-2192. DOI: 10.1109/Ted.2002.803627  0.389
2002 Ito C, Banerjee K, Dutton R. Analysis and design of distributed ESD protection circuits for high-speed mixed-signal and RF ICs Ieee Transactions On Electron Devices. 49: 1444-1454. DOI: 10.1109/Ted.2002.801257  0.404
2002 Oh K, Duvvury C, Banerjee K, Dutton RW. Analysis of gate-bias-induced heating effects in deep-submicron ESD protection designs Ieee Transactions On Device and Materials Reliability. 2: 36-42. DOI: 10.1109/Tdmr.2002.802113  0.421
2002 Banerjee K, Mehrotra A. Analysis of on-chip inductance effects for distributed RLC interconnects Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 21: 904-915. DOI: 10.1109/Tcad.2002.800459  0.373
2002 Mahapatra S, Ionescu AM, Banerjee K. A quasi-analytical SET model for few electron circuit simulation Ieee Electron Device Letters. 23: 366-368. DOI: 10.1109/Led.2002.1004237  0.355
2002 Mahapatra S, Ionescu AM, Banerjee K, Declercq M. SET-based quantiser circuit for digital communications Electronics Letters. 38: 443-445. DOI: 10.1049/El:20020308  0.376
2001 Davis JA, Venkatesan R, Kaloyeros A, Beylansky M, Souri SJ, Banerjee K, Saraswat KC, Rahman A, Reif R, Meindl JD. Interconnect limits on gigascale integration (GSI) in the 21st century Proceedings of the Ieee. 89: 305-322. DOI: 10.1109/5.915376  0.332
2001 Banerjee K, Mehrotra A. Global (interconnect) warming Ieee Circuits and Devices Magazine. 17: 16-32. DOI: 10.1109/101.960685  0.363
1998 Rzepka S, Banerjee K, Meusel E, Hu C. Characterization of self-heating in advanced VLSI interconnect lines based on thermal finite element simulation Ieee Transactions On Components, Packaging, and Manufacturing Technology: Part A. 21: 406-411. DOI: 10.1109/95.725203  0.316
1997 Banerjee K, Amerasekera A, Cheung N, Hu C. High-current failure model for VLSI interconnects under short-pulse stress conditions Ieee Electron Device Letters. 18: 405-407. DOI: 10.1109/55.622511  0.357
1996 Le HA, Banerjee K, McPherson JW. The dependence of W-plug via EM performance on via size Semiconductor Science and Technology. 11: 858-864. DOI: 10.1088/0268-1242/11/6/003  0.31
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