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Sumeet K. Gupta, Ph.D. - Publications

Affiliations: 
2012 Electrical and Computer Engineering Purdue University, West Lafayette, IN, United States 
Area:
Electronics and Electrical Engineering, Nanotechnology
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62 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Saha AK, Gupta SK. Multi-Domain Negative Capacitance Effects in Metal-Ferroelectric-Insulator-Semiconductor/Metal Stacks: A Phase-field Simulation Based Study. Scientific Reports. 10: 10207. PMID 32576840 DOI: 10.1038/S41598-020-66313-1  0.307
2020 Jain S, Gupta SK, Raghunathan A. TiM-DNN: Ternary In-Memory Accelerator for Deep Neural Networks Ieee Transactions On Very Large Scale Integration Systems. 28: 1567-1577. DOI: 10.1109/Tvlsi.2020.2993045  0.376
2020 Liang Y, Zhu Z, Li X, Gupta SK, Datta S, Narayanan V. Mismatch of Ferroelectric Film on Negative Capacitance FETs Performance Ieee Transactions On Electron Devices. 67: 1297-1304. DOI: 10.1109/Ted.2020.2968050  0.331
2020 Chakraborty I, Jaiswal A, Saha AK, Gupta SK, Roy K. Pathways to efficient neuromorphic computing with non-volatile memory technologies Applied Physics Reviews. 7: 021308. DOI: 10.1063/1.5113536  0.547
2019 Liang Y, Zhu Z, Li X, Gupta SK, Datta S, Narayanan V. Utilization of Negative-Capacitance FETs to Boost Analog Circuit Performances Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 27: 2855-2860. DOI: 10.1109/Tvlsi.2019.2932268  0.48
2019 Thirumala SK, Gupta SK. Reconfigurable Ferroelectric Transistor–Part II: Application in Low-Power Nonvolatile Memories Ieee Transactions On Electron Devices. 66: 2780-2788. DOI: 10.1109/Ted.2019.2912562  0.425
2019 Thakuria N, Saha AK, Thirumala SK, Jung B, Gupta SK. Oscillators Utilizing Ferroelectric-Based Transistors and Their Coupled Dynamics Ieee Transactions On Electron Devices. 66: 2415-2423. DOI: 10.1109/Ted.2019.2902107  0.346
2019 Thirumala SK, Gupta SK. Reconfigurable Ferroelectric Transistor—Part I: Device Design and Operation Ieee Transactions On Electron Devices. 66: 2771-2779. DOI: 10.1109/Ted.2019.2897960  0.416
2019 Shen Z, Srinivasa S, Aziz A, Datta S, Narayanan V, Gupta SK. SRAMs and DRAMs With Separate Read–Write Ports Augmented by Phase Transition Materials Ieee Transactions On Electron Devices. 66: 929-937. DOI: 10.1109/Ted.2018.2888913  0.35
2019 Saki AA, Lin SH, Alam M, Thirumala SK, Gupta SK, Ghosh S. A Family of Compact Non-Volatile Flip-Flops With Ferroelectric FET Ieee Transactions On Circuits and Systems I: Regular Papers. 66: 4219-4229. DOI: 10.1109/Tcsi.2019.2927347  0.635
2019 Rangachar Srinivasa S, Ramanathan AK, Li X, Chen W, Gupta SK, Chang M, Ghosh S, Sampson J, Narayanan V. ROBIN: Monolithic-3D SRAM for Enhanced Robustness with In-Memory Computation Support Ieee Transactions On Circuits and Systems I: Regular Papers. 66: 2533-2545. DOI: 10.1109/Tcsi.2019.2897497  0.654
2019 Li X, Wu J, Ni K, George S, Ma K, Sampson J, Gupta SK, Liu Y, Yang H, Datta S, Narayanan V. Design of 2T/Cell and 3T/Cell Nonvolatile Memories with Emerging Ferroelectric FETs Ieee Design & Test of Computers. 36: 39-45. DOI: 10.1109/Mdat.2019.2902094  0.446
2019 Si M, Saha AK, Gao S, Qiu G, Qin J, Duan Y, Jian J, Niu C, Wang H, Wu W, Gupta SK, Ye PD. A ferroelectric semiconductor field-effect transistor Nature Electronics. 2: 580-586. DOI: 10.1038/S41928-019-0338-7  0.427
2018 George S, Li X, Liao MJ, Ma K, Srinivasa S, Mohan K, Aziz A, Sampson J, Gupta SK, Narayanan V. Symmetric 2-D-Memory Access to Multidimensional Data Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 26: 1040-1050. DOI: 10.1109/Tvlsi.2018.2801302  0.378
2018 Srinivasa S, Li X, Chang M, Sampson J, Gupta SK, Narayanan V. Compact 3-D-SRAM Memory With Concurrent Row and Column Data Access Capability Using Sequential Monolithic 3-D Integration Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 26: 671-683. DOI: 10.1109/Tvlsi.2017.2787562  0.41
2018 Liang Y, Li X, Gupta SK, Datta S, Narayanan V. Analysis of DIBL Effect and Negative Resistance Performance for NCFET Based on a Compact SPICE Model Ieee Transactions On Electron Devices. 65: 5525-5529. DOI: 10.1109/Ted.2018.2875661  0.366
2018 Aziz A, Gupta SK. Threshold Switch Augmented STT MRAM: Design Space Analysis and Device-Circuit Co-Design Ieee Transactions On Electron Devices. 65: 5381-5389. DOI: 10.1109/Ted.2018.2873738  0.476
2018 Liang Y, Li X, George S, Srinivasa S, Zhu Z, Gupta SK, Datta S, Narayanan V. Influence of Body Effect on Sample-and-Hold Circuit Design Using Negative Capacitance FET Ieee Transactions On Electron Devices. 65: 3909-3914. DOI: 10.1109/Ted.2018.2852679  0.411
2018 Li X, George S, Liang Y, Ma K, Ni K, Aziz A, Gupta SK, Sampson J, Chang M, Liu Y, Yang H, Datta S, Narayanan V. Lowering Area Overheads for FeFET-Based Energy-Efficient Nonvolatile Flip-Flops Ieee Transactions On Electron Devices. 65: 2670-2674. DOI: 10.1109/Ted.2018.2829348  0.426
2017 Gupta S, Steiner M, Aziz A, Narayanan V, Datta S, Gupta SK. Device-Circuit Analysis of Ferroelectric FETs for Low-Power Logic Ieee Transactions On Electron Devices. 64: 3092-3100. DOI: 10.1109/Ted.2017.2717929  0.391
2017 Li X, Sampson J, Khan A, Ma K, George S, Aziz A, Gupta SK, Salahuddin S, Chang M, Datta S, Narayanan V. Enabling Energy-Efficient Nonvolatile Computing With Negative Capacitance FET Ieee Transactions On Electron Devices. 64: 3452-3458. DOI: 10.1109/Ted.2017.2716338  0.442
2017 Li X, Ma K, George S, Khwa W, Sampson J, Gupta S, Liu Y, Chang M, Datta S, Narayanan V. Design of Nonvolatile SRAM with Ferroelectric FETs for Energy-Efficient Backup and Restore Ieee Transactions On Electron Devices. 64: 3037-3040. DOI: 10.1109/Ted.2017.2707664  0.449
2017 Aziz A, Shukla N, Datta S, Gupta SK. Steep Switching Hybrid Phase Transition FETs (Hyper-FET) for Low Power Applications: A Device-Circuit Co-design Perspective—Part II Ieee Transactions On Electron Devices. 64: 1358-1365. DOI: 10.1109/Ted.2017.2650598  0.395
2017 Aziz A, Shukla N, Datta S, Gupta SK. Steep Switching Hybrid Phase Transition FETs (Hyper-FET) for Low Power Applications: A Device-Circuit Co-design Perspective–Part I Ieee Transactions On Electron Devices. 64: 1350-1357. DOI: 10.1109/ted.2016.2642884  0.302
2017 Li X, George S, Ma K, Tsai W, Aziz A, Sampson J, Gupta SK, Chang M, Liu Y, Datta S, Narayanan V. Advancing Nonvolatile Computing With Nonvolatile NCFET Latches and Flip-Flops Ieee Transactions On Circuits and Systems I: Regular Papers. 64: 2907-2919. DOI: 10.1109/Tcsi.2017.2702741  0.364
2016 Kim MS, Cane-Wissing W, Li X, Sampson J, Datta S, Gupta SK, Narayanan V. Comparative area and parasitics analysis in FinFET and heterojunction vertical TFET standard cells Acm Journal On Emerging Technologies in Computing Systems. 12. DOI: 10.1145/2914790  0.433
2016 George S, Ma K, Aziz A, Li X, Khan A, Salahuddin S, Chang MF, Datta S, Sampson J, Gupta S, Narayanan V. Nonvolatile memory design based on ferroelectric FETs Proceedings - Design Automation Conference. 5. DOI: 10.1145/2897937.2898050  0.394
2016 Aziz A, Gupta SK. Hybrid Multiplexing (HYM) for read- and area-optimized MRAMs with separate read-write paths Ieee Transactions On Nanotechnology. 15: 473-483. DOI: 10.1109/Tnano.2016.2544860  0.426
2016 Srinivasa S, Aziz A, Shukla N, Li X, Sampson J, Datta S, Kulkarni JP, Narayanan V, Gupta SK. Correlated Material Enhanced SRAMs With Robust Low Power Operation Ieee Transactions On Electron Devices. 63: 4744-4752. DOI: 10.1109/Ted.2016.2621125  0.707
2016 Aziz A, Jao N, Datta S, Gupta SK. Analysis of Functional Oxide based Selectors for Cross-Point Memories Ieee Transactions On Circuits and Systems I: Regular Papers. 63: 2222-2235. DOI: 10.1109/Tcsi.2016.2620475  0.396
2016 Aziz A, Ghosh S, Datta S, Gupta SK. Physics-Based Circuit-Compatible SPICE Model for Ferroelectric Transistors Ieee Electron Device Letters. 37: 805-808. DOI: 10.1109/Led.2016.2558149  0.383
2016 George S, Aziz A, Li X, Kim MS, Datta S, Sampson J, Gupta S, Narayanan V. Device circuit Co design of FEFET based logic for low voltage processors Proceedings of Ieee Computer Society Annual Symposium On Vlsi, Isvlsi. 2016: 649-654. DOI: 10.1109/ISVLSI.2016.116  0.397
2015 Shukla N, Thathachary AV, Agrawal A, Paik H, Aziz A, Schlom DG, Gupta SK, Engel-Herbert R, Datta S. A steep-slope transistor based on abrupt electronic phase transition. Nature Communications. 6: 7812. PMID 26249212 DOI: 10.1038/Ncomms8812  0.389
2015 Kumar A, Samanta S, Singh A, Roy M, Singh S, Basu S, Chehimi MM, Roy K, Ramgir NS, Debnath AK, Aswal DK, Gupta SK, Navneethan M, Hayakawa Y. Fast Response and High Sensitivity of ZnO Nanowires - Cobalt Phthalocyanine Heterojunction based H2S Sensor. Acs Applied Materials & Interfaces. PMID 26225901 DOI: 10.1021/acsami.5b03652  0.355
2014 Cho W, Gupta SK, Roy K. Device-Circuit Analysis of Double-Gate MOSFETs and Schottky-Barrier FETs: A Comparison Study for Sub-10-nm Technologies Ieee Transactions On Electron Devices. 61: 4025-4031. DOI: 10.1109/Ted.2014.2364791  0.538
2014 Choday SH, Gupta SK, Roy K. Write-optimized STT-MRAM bit-cells using asymmetrically doped transistors Ieee Electron Device Letters. 35: 1100-1102. DOI: 10.1109/Led.2014.2358998  0.799
2013 Gupta SK, Roy K. (Invited) Spacer Thickness Optimization for FinFET-based Logic and Memories: A Device-Circuit Co-Design Approach Ecs Transactions. 50: 187-192. DOI: 10.1149/05004.0187ecst  0.503
2013 Mojumder NN, Fong X, Augustine C, Gupta SK, Choday SH, Roy K. Dual pillar spin-transfer torque MRAMs for low power applications Acm Journal On Emerging Technologies in Computing Systems. 9. DOI: 10.1145/2463585.2463590  0.753
2013 Gupta SK, Kulkarni JP, Roy K. Tri-mode independent gate finfet-based sram with pass-gate feedback: Technology-circuit co-design for enhanced cell stability Ieee Transactions On Electron Devices. 60: 3696-3704. DOI: 10.1109/Ted.2013.2283235  0.763
2013 Gupta SK, Roy K. Device-Circuit Co-Optimization for Robust Design of FinFET-Based SRAMs Ieee Design & Test. 30: 29-39. DOI: 10.1109/Mdat.2013.2266394  0.548
2013 Goud AA, Gupta SK, Choday SH, Roy K. Atomistic tight-binding based evaluation of impact of gate underlap on source to drain tunneling in 5 nm gate length Si FinFETs Device Research Conference - Conference Digest, Drc. 51-52. DOI: 10.1109/DRC.2013.6633788  0.739
2012 Park SP, Gupta S, Mojumder N, Raghunathan A, Roy K. Future cache design using STT MRAMs for improved energy efficiency: Devices, circuits and architecture Proceedings - Design Automation Conference. 492-497. DOI: 10.1145/2228360.2228447  0.789
2012 Sharad M, Gupta SK, Raghunathan S, Irazoqui PP, Roy K. Low-power architecture for epileptic seizure detection based on reduced complexity DWT Acm Journal On Emerging Technologies in Computing Systems. 8. DOI: 10.1145/2180878.2180882  0.507
2012 Gupta SK, Kulkarni JP, Datta S, Roy K. Heterojunction intra-band tunnel FETs for low-voltage SRAMs Ieee Transactions On Electron Devices. 59: 3533-3542. DOI: 10.1109/Ted.2012.2221127  0.713
2012 Gupta SK, Panagopoulos G, Roy K. NBTI in n-Type SOI Access FinFETs in SRAMs and Its Impact on Cell Stability and Performance Ieee Transactions On Electron Devices. 59: 2603-2609. DOI: 10.1109/Ted.2012.2209182  0.759
2012 Gupta SK, Kulkarni JP, Datta S, Roy K. Dopant straggle-free heterojunction intra-band tunnel (HIBT) FETs with low drain-induced barrier lowering/thinning (DIBL/T) and reduced variation in off current Device Research Conference - Conference Digest, Drc. 55-56. DOI: 10.1109/DRC.2012.6257027  0.709
2011 Raghunathan S, Gupta SK, Markandeya HS, Irazoqui PP, Roy K. Ultra low-power algorithm design for implantable devices: Application to epilepsy prostheses Journal of Low Power Electronics and Applications. 1: 175-203. DOI: 10.3390/Jlpea1010175  0.486
2011 Moradi F, Gupta SK, Panagopoulos G, Wisland DT, Mahmoodi H, Roy K. Asymmetrically Doped FinFETs for Low-Power Robust SRAMs Ieee Transactions On Electron Devices. 58: 4241-4249. DOI: 10.1109/Ted.2011.2169678  0.786
2011 Gupta SK, Park SP, Roy K. Tri-Mode Independent-Gate FinFETs for Dynamic Voltage/Frequency Scalable 6T SRAMs Ieee Transactions On Electron Devices. 58: 3837-3846. DOI: 10.1109/Ted.2011.2166117  0.591
2011 Mojumder NN, Gupta SK, Choday SH, Nikonov DE, Roy K. A three-terminal dual-pillar STT-MRAM for high-performance robust memory applications Ieee Transactions On Electron Devices. 58: 1508-1516. DOI: 10.1109/Ted.2011.2116024  0.78
2011 Goel A, Gupta SK, Roy K. Asymmetric Drain Spacer Extension (ADSE) FinFETs for Low-Power and Robust SRAMs Ieee Transactions On Electron Devices. 58: 296-308. DOI: 10.1109/Ted.2010.2090421  0.691
2011 Fong X, Gupta SK, Mojumder NN, Choday SH, Augustine C, Roy K. KNACK: A hybrid spin-charge mixed-mode simulator for evaluating different genres of spin-transfer torque MRAM bit-cells International Conference On Simulation of Semiconductor Processes and Devices, Sispad. 51-54. DOI: 10.1109/SISPAD.2011.6035047  0.74
2011 Gupta SK, Choday SH, Roy K. Exploration of device-circuit interactions in FinFET-based memories for sub-15nm technologies using a mixed mode quantum simulation framework: Atoms to systems Technical Digest - International Electron Devices Meeting, Iedm. 32.5.1-32.5.4. DOI: 10.1109/IEDM.2011.6131659  0.776
2011 Mojumder NN, Gupta SK, Roy K. Dual Pillar Spin Transfer Torque MRAM with tilted magnetic anisotropy for fast and error-free switching and near-disturb-free read operations Device Research Conference - Conference Digest, Drc. 67-68. DOI: 10.1109/DRC.2011.5994466  0.774
2010 Raghunathan S, Gupta SK, Markandeya HS, Roy K, Irazoqui PP. A hardware-algorithm co-design approach to optimize seizure detection algorithms for implantable applications. Journal of Neuroscience Methods. 193: 106-17. PMID 20713084 DOI: 10.1016/J.Jneumeth.2010.08.008  0.45
2010 Gupta SK, Raychowdhury A, Roy K. Digital computation in subthreshold region for ultralow-power operation: A device-circuit-architecture codesign perspective Proceedings of the Ieee. 98: 160-190. DOI: 10.1109/JPROC.2009.2035060  0.689
2009 Raghunathan S, Gupta SK, Ward MP, Worth RM, Roy K, Irazoqui PP. The design and hardware implementation of a low-power real-time seizure detection algorithm. Journal of Neural Engineering. 6: 056005. PMID 19717893 DOI: 10.1088/1741-2560/6/5/056005  0.499
2009 Gupta SK, Raychowdhury A, Roy K. Compact models considering incomplete voltage swing in complementary metal oxide semiconductor circuits at ultralow voltages: A circuit perspective on limits of switching energy Journal of Applied Physics. 105. DOI: 10.1063/1.3123763  0.681
2009 Roy K, Kulkarni JP, Gupta SK. Device/circuit interactions at 22nm technology node Proceedings - Design Automation Conference. 97-102.  0.713
2006 Kumar MJ, Venkataraman V, Gupta SK. A new grounded lamination gate (GLG) for diminished fringe-capacitance effects in high-κ gate-dielectric MOSFETs Ieee Transactions On Electron Devices. 53: 2578-2581. DOI: 10.1109/Ted.2006.882268  0.416
2006 Kumar MJ, Gupta SK, Venkataraman V. Compact modeling of the effects of parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric nanoscale SOI MOSFETs Ieee Transactions On Electron Devices. 53: 706-711. DOI: 10.1109/Ted.2006.870424  0.388
2005 Kumar MJ, Venkataraman V, Gupta SK. On the parasitic gate capacitance of small-geometry MOSFETs Ieee Transactions On Electron Devices. 52: 1676-1677. DOI: 10.1109/Ted.2005.850630  0.345
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