Year |
Citation |
Score |
2019 |
Douglass AJ, Khatri SP. Fast, Ring-Based Design of 3-D Stacked DRAM Ieee Transactions On Very Large Scale Integration Systems. 27: 1731-1741. DOI: 10.1109/Tvlsi.2019.2892740 |
0.372 |
|
2018 |
Al Kawam A, Datta A, Khatri S. A GPU-CPU heterogeneous algorithm for NGS read alignment International Journal of Computational Biology and Drug Design. 11: 52. DOI: 10.1504/Ijcbdd.2018.10011906 |
0.329 |
|
2018 |
Fairouz A, Abusultan M, Elshennawy A, Khatri SP. Comparing Leakage Reduction Techniques for an Asynchronous Network-on-Chip Router Journal of Low Power Electronics. 14: 414-427. DOI: 10.1166/Jolpe.2018.1571 |
0.309 |
|
2016 |
Fedorov VV, Abusultan M, Khatri SP. FTCAM: An Area-Efficient Flash-Based Ternary CAM Design Ieee Transactions On Computers. 65: 2652-2658. DOI: 10.1109/Tc.2015.2493535 |
0.417 |
|
2014 |
Fedorov VV, Abusultan M, Khatri SP. An area-efficient Ternary CAM design using floating gate transistors 2014 32nd Ieee International Conference On Computer Design, Iccd 2014. 55-60. DOI: 10.1109/ICCD.2014.6974662 |
0.317 |
|
2013 |
Croix JF, Khatri SP, Gulati K. Using gpus to acceleratecad algorithms Ieee Design and Test. 30: 8-16. DOI: 10.1109/Mdat.2013.2250053 |
0.339 |
|
2011 |
Turker DZ, Khatri SP, Sánchez-Sinencio E. A DCVSL delay cell for fast low power frequency synthesis applications Ieee Transactions On Circuits and Systems I: Regular Papers. 58: 1225-1238. DOI: 10.1109/Tcsi.2010.2103170 |
0.352 |
|
2010 |
Jayakumar N, Khatri SP. A simultaneous input vector control and circuit modification technique to reduce leakage with zero delay penalty Acm Transactions On Design Automation of Electronic Systems. 16. DOI: 10.1145/1870109.1870118 |
0.412 |
|
2010 |
Gingl Z, Kish LB, Khatri SP. Towards brain-inspired computing Fluctuation and Noise Letters. 9: 403-412. DOI: 10.1142/S0219477510000332 |
0.362 |
|
2010 |
Singh A, Gulati K, Khatri SP. Minimum leakage vector computation using weighted partial MaxSAT Midwest Symposium On Circuits and Systems. 201-204. DOI: 10.1109/MWSCAS.2010.5548692 |
0.321 |
|
2010 |
Duan C, LaMeres BJ, Khatri SP. On and off-chip crosstalk avoidance in VLSI design On and Off-Chip Crosstalk Avoidance in Vlsi Design. 1-240. DOI: 10.1007/978-1-4419-0947-3 |
0.706 |
|
2009 |
Bollapalli KC, Garg R, Gulati K, Khatri SP. Selective forward body bias for high speed and low power SRAMs Journal of Low Power Electronics. 5: 185-195. DOI: 10.1166/Jolpe.2009.1019 |
0.378 |
|
2009 |
Ekambavanan S, Garg R, Khatri SP, Narayanan KR. Encoding serial graphical data for Energy-Delay Product/energy minimization Journal of Low Power Electronics. 5: 157-172. DOI: 10.1166/Jolpe.2009.1017 |
0.318 |
|
2009 |
Gulati K, Paul S, Khatri SP, Patil S, Jas A. FPGA-based hardware acceleration for Boolean satisfiability Acm Transactions On Design Automation of Electronic Systems. 14. DOI: 10.1145/1497561.1497576 |
0.35 |
|
2009 |
Garg R, Jayakumar N, Khatri SP, Choi GS. Circuit-level design approaches for radiation-hard digital electronics Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 17: 781-792. DOI: 10.1109/Tvlsi.2008.2006795 |
0.386 |
|
2009 |
Duan C, Cordero Calle VH, Khatri SP. Efficient on-chip crosstalk avoidance CODEC design Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 17: 551-560. DOI: 10.1109/Tvlsi.2008.2005313 |
0.377 |
|
2009 |
Paul S, Jayakumar N, Khatri SP. A fast hardware approach for approximate, efficient logarithm and antilogarithm computations Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 17: 269-277. DOI: 10.1109/Tvlsi.2008.2003481 |
0.4 |
|
2009 |
Kish LB, Khatri S, Sethuraman S. Noise-based logic hyperspace with the superposition of 2N states in a single wire Physics Letters, Section a: General, Atomic and Solid State Physics. 373: 1928-1934. DOI: 10.1016/J.Physleta.2009.03.059 |
0.313 |
|
2008 |
Das S, Khatri SP. Resource sharing among mutually exclusive sum-of-product blocks for area reduction Acm Transactions On Design Automation of Electronic Systems. 13. DOI: 10.1145/1367045.1367060 |
0.58 |
|
2008 |
Saluja N, Gulati K, Khatri SP. SAT-based ATPG using multilevel compatible don't-cares Acm Transactions On Design Automation of Electronic Systems. 13. DOI: 10.1145/1344418.1344420 |
0.346 |
|
2008 |
Das S, Khatri SP. A timing-driven synthesis technique for arithmetic product-of-sum expressions Proceedings of the Ieee International Frequency Control Symposium and Exposition. 635-640. DOI: 10.1109/VLSI.2008.19 |
0.337 |
|
2008 |
Das S, Khatri SP. An inversion-based synthesis approach for area and power efficient arithmetic sum-of-products Proceedings of the Ieee International Frequency Control Symposium and Exposition. 653-658. DOI: 10.1109/VLSI.2008.18 |
0.31 |
|
2008 |
Kapoor A, Jayakumar N, Khatri SP. Dynamically de-skewable clock distribution methodology Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 16: 1220-1229. DOI: 10.1109/Tvlsi.2008.2000729 |
0.36 |
|
2008 |
Das S, Khatri SP. A novel hybrid parallel-prefix adder architecture with efficient timing-area characteristic Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 16: 326-331. DOI: 10.1109/Tvlsi.2007.915507 |
0.581 |
|
2008 |
Das S, Khatri SP. A timing-driven approach to synthesize fast barrel shifters Ieee Transactions On Circuits and Systems Ii: Express Briefs. 55: 31-35. DOI: 10.1109/Tcsii.2007.908951 |
0.551 |
|
2008 |
Das S, Khatri SP. A timing-driven synthesis approach of a fast four-stage hybrid adder in Sum-of-Products Midwest Symposium On Circuits and Systems. 507-510. DOI: 10.1109/MWSCAS.2008.4616847 |
0.304 |
|
2008 |
Duan C, Khatri SP. Energy efficient and high speed on-chip ternary bus Proceedings -Design, Automation and Test in Europe, Date. 515-518. DOI: 10.1109/DATE.2008.4484901 |
0.509 |
|
2008 |
Gulati K, Waghmode M, Khatri SP, Shi W. Efficient, scalable hardware engine for Boolean satisfiability and unsatisfiable core extraction Iet Computers and Digital Techniques. 2: 214-229. DOI: 10.1049/Iet-Cdt:20060221 |
0.413 |
|
2008 |
Gulati K, Jayakumar N, Khatri SP, Walker DMH. A probabilistic method to determine the minimum leakage vector for combinational designs in the presence of random PVT variations Integration, the Vlsi Journal. 41: 399-412. DOI: 10.1016/J.Vlsi.2007.10.001 |
0.395 |
|
2007 |
Jayakumar N, Khatri SP. A predictably low-leakage ASIC design style Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 15: 276-285. DOI: 10.1109/Tvlsi.2007.893603 |
0.384 |
|
2007 |
Das S, Khatri SP. Timing-driven decomposition of a fast barrel shifter Midwest Symposium On Circuits and Systems. 574-577. DOI: 10.1109/MWSCAS.2007.4488648 |
0.346 |
|
2007 |
Das S, Khatri SP. Generation of the optimal bit-width topology of the fast hybrid adder in a parallel multiplier Proceedings 2007 Ieee International Conference On Integrated Circuit Design and Technology, Icicdt. 49-54. DOI: 10.1109/ICICDT.2007.4299541 |
0.312 |
|
2007 |
Nagarajan V, Laendner S, Milenkovic O, Jayakumar N, Khatri SP. High-throughput VLSI implementations of iterative decoders and related code construction problems Journal of Vlsi Signal Processing Systems For Signal, Image, and Video Technology. 49: 185-206. DOI: 10.1007/s11265-007-0054-9 |
0.302 |
|
2006 |
Waghmode M, Gulati K, Khatri SP, Shi W. An efficient, scalable hardware engine for Boolean Satisfiability Ieee International Conference On Computer Design, Iccd 2006. 326-331. DOI: 10.1109/ICCD.2006.4380836 |
0.303 |
|
2006 |
Garg R, Jayakumar N, Sanchez M, Gupta A, Gulati K, Khatri SP. A design flow to optimize circuit delay by using standard cells and PLAs Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 2006: 217-222. |
0.303 |
|
2006 |
Garg R, Khatri SP. Generalized buffering of PTL logic stages using boolean division Proceedings - Ieee International Symposium On Circuits and Systems. 5615-5618. |
0.317 |
|
2006 |
LaMeres BJ, Gulati K, Khatri SP. Controlling Inductive Cross-Talk and Power in Off-chip Buses using CODECs Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 2006: 850-855. |
0.682 |
|
2006 |
LaMeres BJ, Garg R, Gulati K, Khatri SP. Impedance matching techniques for VLSI packaging International Engineering Consortium - Designcon 2006. 2: 1009-1030. |
0.691 |
|
2006 |
Duan C, Gulati K, Khatri SP. Memory-based cross-talk canceling CODECs for on-chip buses Proceedings - Ieee International Symposium On Circuits and Systems. 1119-1122. |
0.568 |
|
2006 |
LaMeres BJ, Khatri SP. Bus stuttering: An encoding technique to reduce inductive noise in off-chip data transmission Proceedings -Design, Automation and Test in Europe, Date. 1. |
0.641 |
|
2006 |
Duan C, Khatri SP. Computing during supply voltage switching in DVS enabled real-time processors Proceedings - Ieee International Symposium On Circuits and Systems. 5115-5118. |
0.551 |
|
2005 |
Lameres BJ, Khatri SP. Encoding-based minimization of inductive cross-talk for off-chip data transmission Proceedings -Design, Automation and Test in Europe, Date '05. 1318-1323. DOI: 10.1109/DATE.2005.134 |
0.688 |
|
2004 |
Khatri SP, Sinha S, Brayton RK, Sangiovanni-Vincentelli AL. SPFD-based wire removal in standard-cell and network-of-PLA circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 23: 1020-1030. DOI: 10.1109/Tcad.2004.829821 |
0.706 |
|
2004 |
Duan C, Khatri SP. Exploiting crosstalk to speed up on-chip buses Proceedings - Design, Automation and Test in Europe Conference and Exhibition. 2: 778-783. DOI: 10.1109/DATE.2004.1268974 |
0.504 |
|
2003 |
Gamache B, Pfeffer Z, Khatri SP. A fast ternary CAM design for IP networking applications Proceedings - International Conference On Computer Communications and Networks, Icccn. 2003: 434-439. DOI: 10.1109/ICCCN.2003.1284205 |
0.347 |
|
2002 |
Das S, Khatri SP. An efficient and regular routing methodology for datapath designs using net regularity extraction Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 21: 93-101. DOI: 10.1109/43.974141 |
0.544 |
|
2001 |
Gosti W, Khatri SP, Sangiovanni-Vincentelli AL. Addressing the timing closure problem by integrating logic optimization and placement Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 224-231. |
0.641 |
|
1998 |
Taşıran S, Khatri SP, Yovine S, Brayton RK, Sangiovanni-Vincentelli A. A timed automaton-based method for accurate computation of circuit delay in the presence of cross-talk Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 1522: 149-166. |
0.56 |
|
1996 |
Jain J, Narayan A, Coelho C, Khatri SP, Sangiovanni-Vincentelli A, Brayton RK, Fujita M. Decomposition techniques for efficient ROBDD construction Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 1166: 419-434. DOI: 10.1007/BFb0031825 |
0.65 |
|
1996 |
Brayton RK, Hachtel GD, Sangiovanni-Vincentelli A, Somenzi F, Aziz A, Cheng ST, Edwards SA, Khatri SP, Kukimoto Y, Pardo A, Qadeer S, Ranjan RK, Sarwary S, Shiple TR, Swamy G, et al. VIS Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 1166: 248-256. DOI: 10.1007/BFb0031812 |
0.42 |
|
1996 |
Brayton RK, Somenzi F, Khatri S, Ranjan RK, Villa T, Hachtel GD, Sangiovanni-Vincentelli A, Aziz A, Cheng ST, Edwards S, Kukimoto Y, Pardo A, Qadeer S, Sarwary S, Shiple TR, et al. VIS: A system for verification and synthesis Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 1102: 428-432. DOI: 10.1007/3-540-61474-5_95 |
0.55 |
|
1996 |
Narayan A, Khatri SP, Jain J, Fujita M, Brayton RK, Sangiovanni-Vincentelli A. Study of composition schemes for mixed apply/compose based construction of ROBDDs Proceedings of the Ieee International Conference On Vlsi Design. 249-252. |
0.533 |
|
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