☰

Maciej Ciesielski - Publications

Affiliations: 
Electrical & Computer Engineering University of Massachusetts, Amherst, Amherst, MA 
Area:
Electronics and Electrical Engineering
Website:
https://ece.umass.edu/faculty/maciej-j-ciesielski
Tree Info Similar researchers PubMed Report error

39 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Ciesielski M, Su T, Yasin A, Yu C. Understanding Algebraic Rewriting for Arithmetic Circuit Verification: A Bit-Flow Model Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 39: 1346-1357. DOI: 10.1109/Tcad.2019.2912944  0.411
2019 Yu C, Ciesielski M. Formal Analysis of Galois Field Arithmetic Circuits-Parallel Verification and Reverse Engineering Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 38: 354-365. DOI: 10.1109/Tcad.2018.2808457  0.376
2018 Yu C, Ciesielski M, Mishchenko A. Fast Algebraic Rewriting Based on And-Inverter Graphs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 37: 1907-1911. DOI: 10.1109/Tcad.2017.2772854  0.453
2017 Yu C, Zhang X, Liu D, Ciesielski M, Holcomb D. Incremental SAT-Based Reverse Engineering of Camouflaged Logic Circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 36: 1647-1659. DOI: 10.1109/Tcad.2017.2652220  0.368
2016 Yu C, Ciesielski M, Choudhury M, Sullivan A. DAG-aware logic synthesis of datapaths Proceedings - Design Automation Conference. 5. DOI: 10.1145/2897937.2898000  0.352
2016 Yu C, Brown W, Liu D, Rossi A, Ciesielski M. Formal Verification of Arithmetic Circuits by Function Extraction Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 35: 2131-2142. DOI: 10.1109/Tcad.2016.2547898  0.375
2015 Yu C, Brown W, Ciesielski M. Verification of arithmetic datapath designs using word-level approach - A case study Proceedings - Ieee International Symposium On Circuits and Systems. 2015: 1862-1865. DOI: 10.1109/ISCAS.2015.7169020  0.33
2014 Ciesielski M, Brown W, Liu D, Rossi A. Function extraction from arithmetic bit-level circuits Proceedings of Ieee Computer Society Annual Symposium On Vlsi, Isvlsi. 356-361. DOI: 10.1109/ISVLSI.2014.43  0.301
2013 Kim D, Ciesielski M, Yang S. MULTES: Multilevel temporal-parallel event-driven simulation Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 32: 845-857. DOI: 10.1109/Tcad.2013.2237769  0.324
2013 Gomez-Prado D, Ciesielski M, Tessier R. FPGA latency optimization using system-level transformations and DFG restructuring Proceedings -Design, Automation and Test in Europe, Date. 1553-1558.  0.388
2011 Banerjee S, Mathew J, Mohanty SP, Pradhan DK, Ciesielski MJ. A variation-aware taylor expansion diagram-based approach for nano-CMOS register-transfer level leakage optimization Journal of Low Power Electronics. 7: 471-481. DOI: 10.1166/Jolpe.2011.1160  0.306
2011 Basith MA, Ahmad T, Rossi A, Ciesielski M. Algebraic approach to arithmetic design verification 2011 Formal Methods in Computer-Aided Design, Fmcad 2011. 67-71.  0.348
2010 Gomez-Prado D, Kim D, Ciesielski M, Boutillon E. Retiming arithmetic datapaths using timed Taylor expansion diagrams Proceedings - Ieee International High-Level Design Validation and Test Workshop, Hldvt. 33-39. DOI: 10.1109/HLDVT.2010.5496664  0.316
2009 Ciesielski M, Gomez-Prado D, Ren Q, Guillot J, Boutillon E. Optimization of data-flow computations using canonical TED representation Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 28: 1321-1333. DOI: 10.1109/Tcad.2009.2024708  0.693
2009 Ciesielski M, Guillot J, Gomez-Prado D, Boutillon E. High-level dataflow transformations using taylor expansion diagrams Ieee Design and Test of Computers. 26: 46-57. DOI: 10.1109/Mdt.2009.82  0.688
2009 Ciesielski M, Pradhan DK, Jabir AM. Decision diagrams for verification Practical Design Verification. 173-245. DOI: 10.1017/CBO9780511626913.007  0.322
2009 Gomez-Prado D, Ren Q, Ciesielski M, Guillot J, Boutillon E. Optimizing data flow graphs to minimize hardware implementation Proceedings -Design, Automation and Test in Europe, Date. 117-122.  0.453
2007 Ciesielski M, Askar S, Gomez-Prado D, Guillot J, Boutillon E. Data-flow transformations using taylor expansion diagrams Proceedings -Design, Automation and Test in Europe, Date. 455-460. DOI: 10.1109/DATE.2007.364634  0.679
2006 Ciesielski M, Kalla P, Askar S. Taylor expansion diagrams: A canonical representation for verification of data flow designs Ieee Transactions On Computers. 55: 1188-1201. DOI: 10.1109/Tc.2006.153  0.775
2006 Guillot J, Boutillon E, Ren Q, Ciesielski M, Gomez-Prado D, Askar S. Efficient factorization of DSP transforms using Taylor expansion diagrams Proceedings -Design, Automation and Test in Europe, Date. 1.  0.648
2005 Wo Z, Koren I, Ciesielski MJ. Yield-aware floorplanning Proceedings - Dsd'2005: 8th Euromicro Conference On Digital System Design - Architectures, Methods and Tools. 2005: 247-251. DOI: 10.1109/DSD.2005.80  0.674
2005 Zeng Z, Talupuru KR, Ciesielski M. Functional test generation based on word-level SAT Journal of Systems Architecture. 51: 488-511. DOI: 10.1016/J.Sysarc.2004.10.006  0.622
2005 Wo Z, Koren I, Ciesielski M. An ILP formulation for yield-driven architectural synthesis Proceedings - Ieee International Symposium On Defect and Fault Tolerance in Vlsi Systems. 12-20.  0.747
2004 Gomez-Prado D, Ren Q, Askar S, Ciesielski M, Boutillon E. Variable ordering for taylor expansion diagrams Proceedings - Ieee International High-Level Design Validation and Test Workshop, Hldvt. 55-59. DOI: 10.1109/HLDVT.2004.1431235  0.602
2004 Fey G, Drechsler R, Ciesielski M. Algorithms for Taylor expansion diagrams Proceedings of the International Symposium On Multiple-Valued Logic. 235-240.  0.329
2003 Pradhan DK, Askar S, Ciesielski M. Mathematical framework for representing discrete functions as word-level polynomials Proceedings - Ieee International High-Level Design Validation and Test Workshop, Hldvt. 2003: 135-139. DOI: 10.1109/HLDVT.2003.1252487  0.632
2002 Ciesielski M, Askar S, Levitin S. Analytical approach to layout generation of datapath cells Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 21: 1480-1488. DOI: 10.1109/Tcad.2002.804376  0.667
2002 Yang C, Ciesielski M. BDS: A BDD-based logic optimization system Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 21: 866-876. DOI: 10.1109/Tcad.2002.1013899  0.526
2002 Kalla P, Ciesielski M. A comprehensive approach to the partial scan problem using implicit state enumeration Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 21: 810-826. DOI: 10.1109/Tcad.2002.1013894  0.626
2002 Kalla P, Ciesielski M, Boutillon E, Martin E. High-level design verification using Taylor Expansion Diagrams: First results Proceedings - Ieee International High-Level Design Validation and Test Workshop, Hldvt. 2002: 13-17. DOI: 10.1109/HLDVT.2002.1224421  0.685
2002 Ciesielski MJ, Kalla P, Zheng Z, Rouzeyre B. Taylor expansion diagrams: A compact, canonical representation with applications to symbolic verification Proceedings -Design, Automation and Test in Europe, Date. 285-289. DOI: 10.1109/DATE.2002.998286  0.694
2001 Ciesielski M, Kalla P, Zeng Z, Rouzeyre B. Taylor expansion diagrams: A new representation for RTL verification Proceedings - Ieee International High-Level Design Validation and Test Workshop, Hldvt. 2001: 70-75. DOI: 10.1109/HLDVT.2001.972810  0.673
2001 Zeng Z, Kalla P, Ciesielski M. LPSAT: A unified approach to RTL satisfiability Proceedings -Design, Automation and Test in Europe, Date. 398-402. DOI: 10.1109/DATE.2001.915055  0.669
2001 Kalla P, Zeng Z, Ciesielski MJ. Strategies for solving the Boolean satisfiability problem using binary decision diagrams Journal of Systems Architecture. 47: 491-503. DOI: 10.1016/S1383-7621(01)00011-X  0.671
2000 Bommu S, O'Neill N, Ciesielski M. Retiming-based factorization for sequential logic optimization Acm Transactions On Design Automation of Electronic Systems. 5: 373-398. DOI: 10.1145/348019.348068  0.426
2000 Kalla P, Zeng Z, Ciesielski MJ, Huang C. A BDD-based satisfiability infrastructure using the unate recursive paradigm Proceedings -Design, Automation and Test in Europe, Date. 232-236. DOI: 10.1109/DATE.2000.840044  0.601
1999 Kalla P, Ciesielski MJ. Performance driven resynthesis by exploiting retiming-induced state register equivalence Proceedings -Design, Automation and Test in Europe, Date. 638-642. DOI: 10.1109/DATE.1999.761196  0.619
1992 Hasan Z, Harrison D, Ciesielski M. A fast partitioning method for PLA-based FPGAs Ieee Design & Test of Computers. 9: 34-39. DOI: 10.1109/54.173331  0.35
1989 Perkowski M, Driscoll M, Liu J, Smith D, Brown J, Yang L, Shamsapour A, Helliwell M, Falkowski B, Wu P, Ciesielski M, Sarabi A. Integration of logic synthesis and high-level synthesis into the DIADES design automation system Proceedings - Ieee International Symposium On Circuits and Systems. 2: 748-751.  0.321
Show low-probability matches.