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Fabrizio Lombardi - Publications

Affiliations: 
Electrical and Computer Engineering Northeastern University, Boston, MA, United States 
Area:
Computer Science
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201 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Liu S, Reviriego P, Guo J, Han J, Lombardi F. Exploiting Asymmetry in eDRAM Errors for Redundancy-Free Error-Tolerant Design Ieee Transactions On Emerging Topics in Computing. 1-1. DOI: 10.1109/Tetc.2019.2960491  0.349
2020 Reviriego P, Martinez J, Rottenstreich O, Liu S, Lombardi F. Remove Minimum (RM): An Error-Tolerant Scheme for Cardinality Estimate by HyperLogLog Ieee Transactions On Dependable and Secure Computing. 1-1. DOI: 10.1109/Tdsc.2020.3013746  0.318
2020 Chen K, Liu W, Han J, Lombardi F. Profile-Based Output Error Compensation for Approximate Arithmetic Circuits Ieee Transactions On Circuits and Systems I-Regular Papers. 1-12. DOI: 10.1109/Tcsi.2020.2996567  0.373
2020 Guo J, Liu S, Zhu L, Lombardi F. Design and Evaluation of Low-Complexity Radiation Hardened CMOS Latch for Double-Node Upset Tolerance Ieee Transactions On Circuits and Systems. 67: 1925-1935. DOI: 10.1109/Tcsi.2020.2973676  0.317
2020 Liu S, Reviriego P, Lombardi F. Codes for Limited Magnitude Error Correction in Multilevel Cell Memories Ieee Transactions On Circuits and Systems I-Regular Papers. 67: 1615-1626. DOI: 10.1109/Tcsi.2019.2961847  0.326
2020 Li J, Liu S, Reviriego P, Xiao L, Lombardi F. Scheme for periodical concurrent fault detection in parallel CRC circuits Iet Computers and Digital Techniques. 14: 80-85. DOI: 10.1049/Iet-Cdt.2018.5183  0.361
2020 Waris H, Wang C, Liu W, Lombardi F. AxSA: On the Design of High-Performance and Power-Efficient Approximate Systolic Arrays for Matrix Multiplication Journal of Signal Processing Systems. 1-11. DOI: 10.1007/S11265-020-01582-7  0.328
2019 Liu W, Zhang L, Zhang Z, Gu C, Wang C, O'neill M, Lombardi F. XOR-Based Low-Cost Reconfigurable PUFs for IoT Security Acm Transactions in Embedded Computing Systems. 18: 25. DOI: 10.1145/3274666  0.356
2019 Guo J, Liu S, Zhu L, Lombardi F. A CMOS Majority Logic Gate and its Application to One-Step ML Decodable Codes Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 27: 2620-2628. DOI: 10.1109/Tvlsi.2019.2924721  0.406
2019 Liu Y, Liu L, Lombardi F, Han J. An Energy-Efficient and Noise-Tolerant Recurrent Neural Network Using Stochastic Computing Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 27: 2213-2221. DOI: 10.1109/Tvlsi.2019.2920152  0.317
2019 Liu S, Chen K, Reviriego P, Liu W, Louri A, Lombardi F. Reduced Precision Redundancy for Reliable Processing of Data Ieee Transactions On Emerging Topics in Computing. 1-1. DOI: 10.1109/Tetc.2019.2947617  0.409
2019 Gu C, Liu W, Cui Y, Hanley N, O'Neill M, Lombardi F. A Flip-Flop Based Arbiter Physical Unclonable Function (APUF) Design with High Entropy and Uniqueness for FPGA Implementation Ieee Transactions On Emerging Topics in Computing. 1-1. DOI: 10.1109/Tetc.2019.2935465  0.315
2019 Liu W, Zhang T, McLarnon E, O'Neill M, Montuschi P, Lombardi F. Design and Analysis of Majority Logic Based Approximate Adders and Multipliers Ieee Transactions On Emerging Topics in Computing. 1-1. DOI: 10.1109/Tetc.2019.2929100  0.425
2019 Liu S, Reviriego P, Lombardi F. Detection of Limited Magnitude Errors in Emerging Multilevel Cell Memories by One-Bit Parity (OBP) or Two-Bit Parity (TBP) Ieee Transactions On Emerging Topics in Computing. 1-1. DOI: 10.1109/Tetc.2019.2922631  0.383
2019 Liu W, Liao Q, Qiao F, Xia W, Wang C, Lombardi F. Approximate Designs for Fast Fourier Transform (FFT) With Application to Speech Recognition Ieee Transactions On Circuits and Systems I: Regular Papers. 66: 4727-4739. DOI: 10.1109/Tcsi.2019.2933321  0.338
2019 Huang J, Nandha Kumar T, Almurib HAF, Lombardi F. A Deterministic Low-Complexity Approximate (Multiplier-Less) Technique for DCT Computation Ieee Transactions On Circuits and Systems I: Regular Papers. 66: 3001-3014. DOI: 10.1109/Tcsi.2019.2902415  0.33
2019 Jiang H, Liu L, Jonker PP, Elliott DG, Lombardi F, Han J. A High-Performance and Energy-Efficient FIR Adaptive Filter Using Approximate Distributed Arithmetic Circuits Ieee Transactions On Circuits and Systems I: Regular Papers. 66: 313-326. DOI: 10.1109/Tcsi.2018.2856513  0.352
2019 Jiang H, Liu C, Lombardi F, Han J. Low-Power Approximate Unsigned Multipliers With Configurable Error Recovery Ieee Transactions On Circuits and Systems I: Regular Papers. 66: 189-202. DOI: 10.1109/Tcsi.2018.2856245  0.397
2019 Jiang H, Liu L, Lombardi F, Han J. Low-Power Unsigned Divider and Square Root Circuit Designs Using Adaptive Approximation Ieee Transactions On Computers. 68: 1635-1646. DOI: 10.1109/Tc.2019.2916817  0.327
2019 Reviriego P, Liu S, Rottenstreich O, Lombardi F. Two Bit Overlap: A Class of Double Error Correction One Step Majority Logic Decodable Codes Ieee Transactions On Computers. 68: 798-803. DOI: 10.1109/Tc.2018.2890651  0.369
2019 Liu W, Cao T, Yin P, Zhu Y, Wang C, Swartzlander EE, Lombardi F. Design and Analysis of Approximate Redundant Binary Multipliers Ieee Transactions On Computers. 68: 804-819. DOI: 10.1109/Tc.2018.2890222  0.42
2019 Chen K, Chen L, Reviriego P, Lombardi F. Efficient Implementations of Reduced Precision Redundancy (RPR) Multiply and Accumulate (MAC) Ieee Transactions On Computers. 68: 784-790. DOI: 10.1109/Tc.2018.2885044  0.432
2019 Namba K, Lombardi F. Coding for Write Latency Reduction in a Multi-Level Cell (MLC) Phase Change Memory (PCM) Ieee Transactions On Computers. 68: 301-306. DOI: 10.1109/Tc.2018.2868928  0.337
2019 Huang J, Kumar TN, Abbas H, Lombardi F. Approximate computing using frequency upscaling Iet Circuits, Devices & Systems. 13: 1018-1026. DOI: 10.1049/Iet-Cds.2018.5422  0.345
2018 Namba K, Lombardi F. On Coding for Endurance Enhancement and Error Control of Phase Change Memories With Write Latency Reduction Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 26: 230-238. DOI: 10.1109/Tvlsi.2017.2766362  0.355
2018 Liu W, Xu J, Wang D, Wang C, Montuschi P, Lombardi F. Design and Evaluation of Approximate Logarithmic Multipliers for Low Power Error-Tolerant Applications Ieee Transactions On Circuits and Systems I: Regular Papers. 65: 2856-2868. DOI: 10.1109/Tcsi.2018.2792902  0.4
2018 Namba K, Lombardi F. A Single and Adjacent Error Correction Code for Fast Decoding of Critical Bits Ieee Transactions On Computers. 67: 1525-1531. DOI: 10.1109/Tc.2018.2821688  0.339
2018 Liu Y, Liu S, Wang Y, Lombardi F, Han J. A Stochastic Computational Multi-Layer Perceptron with Backward Propagation Ieee Transactions On Computers. 67: 1273-1286. DOI: 10.1109/Tc.2018.2817237  0.344
2018 Almurib HA, Kumar TN, Lombardi F. Approximate DCT Image Compression Using Inexact Computing Ieee Transactions On Computers. 67: 149-159. DOI: 10.1109/Tc.2017.2731770  0.337
2018 Liu Y, Wang Y, Lombardi F, Han J. An Energy-Efficient Online-Learning Stochastic Computational Deep Belief Network Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 8: 454-465. DOI: 10.1109/Jetcas.2018.2852705  0.325
2017 Jiang H, Liu C, Liu L, Lombardi F, Han J. A Review, Classification, and Comparative Evaluation of Approximate Arithmetic Circuits Acm Journal On Emerging Technologies in Computing Systems. 13: 1-34. DOI: 10.1145/3094124  0.369
2017 Junsangsri P, Han J, Lombardi F. Design and Comparative Evaluation of a PCM-Based CAM (Content Addressable Memory) Cell Ieee Transactions On Nanotechnology. 16: 359-363. DOI: 10.1109/Tnano.2017.2649547  0.311
2017 Cui X, Dong W, Liu W, Swartzlander EE, Lombardi F. High Performance Parallel Decimal Multipliers Using Hybrid BCD Codes Ieee Transactions On Computers. 66: 1994-2004. DOI: 10.1109/Tc.2017.2706262  0.361
2017 Pudi V, Sridharan K, Lombardi F. Majority Logic Formulations for Parallel Adder Designs at Reduced Delay and Circuit Complexity Ieee Transactions On Computers. 66: 1824-1830. DOI: 10.1109/Tc.2017.2696524  0.363
2017 Liu W, Qian L, Wang C, Jiang H, Han J, Lombardi F. Design of Approximate Radix-4 Booth Multipliers for Error-Tolerant Computing Ieee Transactions On Computers. 66: 1435-1441. DOI: 10.1109/Tc.2017.2672976  0.407
2017 Chen K, Han J, Lombardi F. Two Approximate Voting Schemes for Reliable Computing Ieee Transactions On Computers. 66: 1227-1239. DOI: 10.1109/Tc.2017.2653780  0.347
2017 Yin P, Wang C, Liu W, Swartzlander EE, Lombardi F. Designs of Approximate Floating-Point Multipliers with Variable Accuracy for Error-Tolerant Applications Journal of Signal Processing Systems. 90: 641-654. DOI: 10.1007/S11265-017-1280-4  0.398
2017 Cui X, Liu W, Wang S, Swartzlander EE, Lombardi F. Design of High-Speed Wide-Word Hybrid Parallel-Prefix/Carry-Select and Skip Adders Journal of Signal Processing Systems. 90: 409-419. DOI: 10.1007/S11265-017-1249-3  0.353
2016 Junsangsri P, Han J, Lombardi F. Logic-in-Memory With a Nonvolatile Programmable Metallization Cell Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 24: 521-529. DOI: 10.1109/Tvlsi.2015.2411258  0.314
2016 Zhu P, Han J, Liu L, Lombardi F. Reliability Evaluation of Phased-Mission Systems Using Stochastic Computation Ieee Transactions On Reliability. 65: 1612-1623. DOI: 10.1109/Tr.2016.2570565  0.309
2016 Namba K, Lombardi F. High-Speed Parallel Decodable Nonbinary Single-Error Correcting (SEC) Codes Ieee Transactions On Device and Materials Reliability. 16: 30-37. DOI: 10.1109/Tdmr.2015.2507983  0.379
2016 Namba K, Lombardi F. Parallel Decodable Multi-Level Unequal Burst Error Correcting Codes for Memories of Approximate Systems Ieee Transactions On Computers. 65: 3794-3801. DOI: 10.1109/Tc.2016.2550449  0.392
2016 Jiang H, Han J, Qiao F, Lombardi F. Approximate Radix-8 Booth Multipliers for Low-Power and High-Performance Operation Ieee Transactions On Computers. 65: 2638-2644. DOI: 10.1109/Tc.2015.2493547  0.35
2016 Wei W, Namba K, Kim Y, Lombardi F. A Novel Scheme for Tolerating Single Event/Multiple Bit Upsets (SEU/MBU) in Non-Volatile Memories Ieee Transactions On Computers. 65: 781-790. DOI: 10.1109/Tc.2015.2462811  0.396
2016 Cui X, Liu W, Chen X, Swartzlander EE, Lombardi F. A Modified Partial Product Generator for Redundant Binary Multipliers Ieee Transactions On Computers. 65: 1165-1171. DOI: 10.1109/Tc.2015.2441711  0.366
2016 Almurib HAF, Lombardi F, Kumar TN. Design and evaluation of a memristor-based look-up table for non-volatile field programmable gate arrays Iet Circuits, Devices & Systems. 10: 292-300. DOI: 10.1049/Iet-Cds.2015.0217  0.361
2016 Kumar TN, Almurib HAF, Lombardi F. Design of a memristor-based look-up table (LUT) for low-energy operation of FPGAs Integration. 55: 1-11. DOI: 10.1016/J.Vlsi.2016.02.005  0.348
2016 Cho G, Lombardi F. Design and process variation analysis of CNTFET-based ternary memory cells Integration, the Vlsi Journal. 54: 97-108. DOI: 10.1016/J.Vlsi.2016.02.003  0.517
2016 Junsangsri P, Han J, Lombardi F. Design of a hybrid non-volatile SRAM cell for concurrent SEU detection and correction Integration, the Vlsi Journal. 52: 156-167. DOI: 10.1016/J.Vlsi.2015.09.005  0.385
2015 Han J, Leung E, Liu L, Lombardi F. A Fault-Tolerant Technique Using Quadded Logic and Quadded Transistors Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 23: 1562-1566. DOI: 10.1109/Tvlsi.2014.2341610  0.406
2015 Zhu P, Han J, Liu L, Lombardi F. A Stochastic Approach for the Analysis of Dynamic Fault Trees With Spare Gates Under Probabilistic Common Cause Failures Ieee Transactions On Reliability. 64: 878-892. DOI: 10.1109/Tr.2015.2419214  0.348
2015 Namba K, Lombardi F. A Single and Adjacent Symbol Error-Correcting Parallel Decoder for Reed–Solomon Codes Ieee Transactions On Device and Materials Reliability. 15: 75-81. DOI: 10.1109/Tdmr.2014.2379513  0.398
2015 Namba K, Lombardi F. Parallel Decodable Two-Level Unequal Burst Error Correcting Codes Ieee Transactions On Computers. 64: 2902-2911. DOI: 10.1109/Tc.2014.2378290  0.367
2015 Namba K, Lombardi F. Non-Binary Orthogonal Latin Square Codes for a Multilevel Phase Charge Memory (PCM) Ieee Transactions On Computers. 64: 2092-2097. DOI: 10.1109/Tc.2014.2346182  0.334
2015 Momeni A, Han J, Montuschi P, Lombardi F. Design and analysis of approximate compressors for multiplication Ieee Transactions On Computers. 64: 984-994. DOI: 10.1109/Tc.2014.2308214  0.393
2014 Wei W, Namba K, Han J, Lombardi F. Design of a Nonvolatile 7T1R SRAM Cell for Instant-on Operation Ieee Transactions On Nanotechnology. 13: 905-916. DOI: 10.1109/Tnano.2014.2329915  0.331
2014 Liang J, Chen L, Han J, Lombardi F. Design and Evaluation of Multiple Valued Logic Gates Using Pseudo N-Type Carbon Nanotube FETs Ieee Transactions On Nanotechnology. 13: 695-708. DOI: 10.1109/Tnano.2014.2316000  0.348
2014 Namba K, Pontarelli S, Ottavi M, Lombardi F. A Single-Bit and Double-Adjacent Error Correcting Parallel Decoder for Multiple-Bit Error Correcting BCH Codes Ieee Transactions On Device and Materials Reliability. 14: 664-671. DOI: 10.1109/Tdmr.2014.2309935  0.41
2014 Namba K, Lombardi F. Concurrent Error Detection of Binary and Nonbinary OLS Parallel Decoders Ieee Transactions On Device and Materials Reliability. 14: 112-120. DOI: 10.1109/Tdmr.2014.2300101  0.421
2014 Cho G, Lombardi F. Circuit-Level Simulation of a CNTFET With Unevenly Positioned CNTs by Linear Programming Ieee Transactions On Device and Materials Reliability. 14: 234-244. DOI: 10.1109/Tdmr.2013.2279154  0.533
2014 Lu Y, Lombardi F, Pontarelli S, Ottavi M. Design and Analysis of Single-Event Tolerant Slave Latches for Enhanced Scan Delay Testing Ieee Transactions On Device and Materials Reliability. 14: 333-343. DOI: 10.1109/Tdmr.2013.2266543  0.383
2014 Almurib HA, Nandha Kumar T, Lombardi F. Scalable Application-Dependent Diagnosisof Interconnects of SRAM-Based FPGAs Ieee Transactions On Computers. 63: 1540-1550. DOI: 10.1109/Tc.2013.34  0.372
2014 Han J, Chen H, Liang J, Zhu P, Yang Z, Lombardi F. A Stochastic Computational Approach for Accurate and Efficient Reliability Evaluation Ieee Transactions On Computers. 63: 1336-1350. DOI: 10.1109/Tc.2012.276  0.4
2014 Wei W, Han J, Lombardi F. Robust HSPICE modeling of a single electron turnstile Microelectronics Journal. 45: 394-407. DOI: 10.1016/J.Mejo.2014.01.014  0.331
2013 Feng W, Lombardi F, Almurib HAF, Kumar TN. Testing a Nanocrossbar for Multiple Fault Detection Ieee Transactions On Nanotechnology. 12: 477-485. DOI: 10.1109/Tnano.2013.2252470  0.347
2013 Junsangsri P, Lombardi F. Design of a Hybrid Memory Cell Using Memristance and Ambipolarity Ieee Transactions On Nanotechnology. 12: 71-80. DOI: 10.1109/Tnano.2012.2229715  0.314
2013 Wei W, Han J, Lombardi F. Design and Evaluation of a Hybrid Memory Cell by Single-Electron Transfer Ieee Transactions On Nanotechnology. 12: 57-70. DOI: 10.1109/Tnano.2012.2228880  0.318
2013 Liang J, Han J, Lombardi F. Analysis of Error Masking and Restoring Properties of Sequential Circuits Ieee Transactions On Computers. 62: 1694-1704. DOI: 10.1109/Tc.2012.147  0.409
2013 Liang J, Han J, Lombardi F. New Metrics for the Reliability of Approximate and Probabilistic Adders Ieee Transactions On Computers. 62: 1760-1771. DOI: 10.1109/Tc.2012.146  0.412
2013 Kumar TN, Lombardi F. A Novel Heuristic Method for Application-Dependent Testing of a SRAM-Based FPGA Interconnect Ieee Transactions On Computers. 62: 163-172. DOI: 10.1109/Tc.2011.247  0.389
2013 Nandha Kumar T, Almurib HAF, Lombardi F. Single-configuration fault detection in application-dependent testing of field programmable gate array interconnects Iet Computers & Digital Techniques. 7: 132-141. DOI: 10.1049/Iet-Cdt.2012.0117  0.383
2013 Cho G, Lombardi F. On the Delay of a CNTFET with Undeposited CNTs by Gate Width Adjustment Journal of Electronic Testing. 29: 261-273. DOI: 10.1007/S10836-013-5388-6  0.511
2012 Lin S, Kim Y, Lombardi F. Design of a Ternary Memory Cell Using CNTFETs Ieee Transactions On Nanotechnology. 11: 1019-1025. DOI: 10.1109/Tnano.2012.2211614  0.327
2012 Lin S, Kim Y, Lombardi F. Analysis and Design of Nanoscale CMOS Storage Elements for Single-Event Hardening With Multiple-Node Upset Ieee Transactions On Device and Materials Reliability. 12: 68-77. DOI: 10.1109/Tdmr.2011.2167233  0.334
2011 Mashreghian Arani Z, Hashempour M, Lombardi F. Optimum coding framework for error detection in the self-assembly of the Sierpinski triangle. Iet Nanobiotechnology / Iet. 5: 61-8. PMID 21913787 DOI: 10.1049/Iet-Nbt.2010.0037  0.739
2011 Lin S, Kim Y, Lombardi F. Design and Performance Evaluation of Radiation Hardened Latches for Nanoscale CMOS Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 19: 1315-1319. DOI: 10.1109/Tvlsi.2010.2047954  0.404
2011 Lin S, Kim Y, Lombardi F. A 11-Transistor Nanoscale CMOS Memory Cell for Hardening to Soft Errors Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 19: 900-904. DOI: 10.1109/Tvlsi.2010.2043271  0.335
2011 Ottavi M, Pontarelli S, DeBenedictis EP, Salsano A, Frost-Murphy S, Kogge PM, Lombardi F. Partially reversible pipelined QCA circuits: Combining low power with high throughput Ieee Transactions On Nanotechnology. 10: 1383-1393. DOI: 10.1109/Tnano.2011.2147796  0.34
2011 Hashempour M, Arani ZM, Lombardi F. Counting by DNA self-assembly in the presence of rotated tiles Ieee Transactions On Nanotechnology. 10: 632-638. DOI: 10.1109/Tnano.2010.2059710  0.71
2011 Lin S, Kim Y, Lombardi F. CNTFET-Based Design of Ternary Logic Gates and Arithmetic Circuits Ieee Transactions On Nanotechnology. 10: 217-225. DOI: 10.1109/Tnano.2009.2036845  0.36
2011 Cho G, Kim Y, Lombardi F. Modeling Undeposited CNTs for CNTFET Operation Ieee Transactions On Device and Materials Reliability. 11: 263-272. DOI: 10.1109/Tdmr.2011.2123896  0.513
2011 Ma X, Hashempour M, Han J, Lombardi F. Modeling errors in synthesized tile sets for template manufacturing by DNA self-assembly Proceedings of the Ieee Conference On Nanotechnology. 1707-1712. DOI: 10.1109/NANO.2011.6144290  0.712
2010 Hashempour M, Arani ZM, Lombardi F. Modeling gross damage in tile-based nanomanufacturing by DNA self-assembly. Ieee Transactions On Nanobioscience. 9: 193-203. PMID 20805045 DOI: 10.1109/Tnb.2010.2053047  0.718
2010 Hashempour M, Mashreghian Arani Z, Lombardi F. Parallel growth and healing of DNA self-assembly for interconnects. Iet Nanobiotechnology / Iet. 4: 19-28. PMID 20170255 DOI: 10.1049/Iet-Nbt.2009.0013  0.73
2010 Ma X, Hashempour M, Wang L, Lombardi F. Manufacturing yield of QCA circuits by synthesized DNA self-assembled templates Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 275-280. DOI: 10.1145/1785481.1785546  0.686
2010 Lin S, Kim Y, Lombardi F. Design of a CNTFET-Based SRAM Cell by Dual-Chirality Selection Ieee Transactions On Nanotechnology. 9: 30-37. DOI: 10.1109/Tnano.2009.2025128  0.328
2010 Hashempour M, Arani ZM, Lombardi F. Multiple error detection in DNA self-assembly using coded tiles Ieee Transactions On Circuits and Systems Ii: Express Briefs. 57: 725-729. DOI: 10.1109/Tcsii.2010.2058490  0.739
2010 Arani ZM, Hashempour M, Lombardi F. An analytical error model for pattern clipping in DNA self-assembly Proceedings - Ieee International Symposium On Defect and Fault Tolerance in Vlsi Systems. 7-15. DOI: 10.1109/DFT.2010.8  0.726
2010 Lin S, Kim Y, Lombardi F. Design and analysis of a 32 nm PVT tolerant CMOS SRAM cell for low leakage and high stability Integration. 43: 176-187. DOI: 10.1016/J.Vlsi.2010.01.003  0.332
2009 Tang W, Wang L, Lombardi F. A defect/error-tolerant nanosystem architecture for DSP Acm Journal On Emerging Technologies in Computing Systems. 5: 1-22. DOI: 10.1145/1629091.1629094  0.446
2009 Kim KK, Kim Y, Lombardi F. A Novel Statistical Timing and Leakage Power Characterization of Partially Depleted Silicon-on-Insulator Gates Ieee Transactions On Instrumentation and Measurement. 58: 401-410. DOI: 10.1109/Tim.2008.2003322  0.342
2009 Arani ZM, Hashempour M, Lombardi F. A coding framework for DNA self-assembly 2009 Ieee/Acm International Symposium On Nanoscale Architectures, Nanoarch 2009. 15-20. DOI: 10.1109/NANOARCH.2009.5226361  0.73
2009 Ma X, Hashempour M, Kim YB, Lombardi F. Errors in DNA self-assembly by synthesized tile sets Proceedings - Ieee International Symposium On Defect and Fault Tolerance in Vlsi Systems. 112-120. DOI: 10.1109/DFT.2009.14  0.717
2009 Arani ZM, Hashempour M, Lombardi F. Coded DNA self-assembly for error detection/location Proceedings - Ieee International Symposium On Defect and Fault Tolerance in Vlsi Systems. 103-111. DOI: 10.1109/DFT.2009.13  0.726
2009 Hashempour M, Mashreghian Arani Z, Lombardi F. Healing DNA self-assemblies using punctures Journal of Electronic Testing: Theory and Applications (Jetta). 25: 25-37. DOI: 10.1007/S10836-008-5082-2  0.733
2008 Hashempour M, Mashreghian Arani Z, Lombardi F. Healing assessment of tile sets for error tolerance in DNA self-assembly. Iet Nanobiotechnology / Iet. 2: 81-92. PMID 19045841 DOI: 10.1049/Iet-Nbt:20080002  0.738
2008 Hashempour M, Arani ZM, Lombardi F. Analysis of punctures in DNA self-assembly under forward growth. Ieee Transactions On Nanobioscience. 7: 120-32. PMID 18556260 DOI: 10.1109/Tnb.2008.2000743  0.746
2008 Ma X, Huang J, Lombardi F. Error tolerant DNA self-assembly using (2k - 1)x(2k - 1) snake tile sets. Ieee Transactions On Nanobioscience. 7: 56-64. PMID 18334456 DOI: 10.1109/Tnb.2008.2000150  0.544
2008 Ma X, Huang J, Lombardi F. A model for computing and energy dissipation of molecular QCA devices and circuits Acm Journal On Emerging Technologies in Computing Systems. 3: 1-30. DOI: 10.1145/1324177.1324180  0.49
2008 Hashempour M, Arani ZM, Lombardi F. A metric for assessing the error tolerance of tile sets for punctured DNA self-assemblies Proceedings of the Ieee Vlsi Test Symposium. 275-282. DOI: 10.1109/VTS.2008.12  0.724
2008 Ma X, Lombardi F. Synthesis of Tile Sets for DNA Self-Assembly Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 963-967. DOI: 10.1109/Tcad.2008.917973  0.379
2008 Hosseinabady M, Sharifi S, Lombardi F, Navabi Z. A Selective Trigger Scan Architecture for VLSI Testing Ieee Transactions On Computers. 57: 316-328. DOI: 10.1109/Tc.2007.70806  0.35
2008 Arani ZM, Hashempour M, Lombardi F. A graph model for tile sets in DNA self-assembly Proceedings - Ieee International Workshop On Design and Test of Nano Devices, Circuits and Systems, Ndcs 2008. 77-80. DOI: 10.1109/NDCS.2008.11  0.698
2008 Hashempour M, Arani ZM, Lombardi F. Robust self-assembly of interconnects by parallel DNA growth 2007 Ieee International Symposium On Nanoscale Architectures, Nanoarch. 70-76. DOI: 10.1109/NANOARCH.2007.4400860  0.73
2008 Hashempour H, Lombardi F. Device Model for Ballistic CNFETs Using the First Conducting Band Ieee Design & Test of Computers. 25: 178-186. DOI: 10.1109/Mdt.2008.34  0.325
2008 Hashempour M, Arani ZM, Lombardi F. A tile-based error model for forward growth of DNA self-assembly Proceedings - Ieee International Symposium On Defect and Fault Tolerance in Vlsi Systems. 516-524. DOI: 10.1109/DFT.2008.15  0.733
2008 Fukushi M, Horiguchi S, Demoracski L, Lombardi F. An Efficient Framework for Scalable Defect Isolation in Large Scale Networks of DNA Self-Assembly Journal of Electronic Testing. 25: 11-23. DOI: 10.1007/S10836-008-5086-Y  0.381
2008 Ma X, Huang J, Metra C, Lombardi F. Detecting Multiple Faults in One-Dimensional Arrays of Reversible QCA Gates Journal of Electronic Testing. 25: 39-54. DOI: 10.1007/S10836-008-5078-Y  0.502
2008 Ma X, Huang J, Metra C, Lombardi F. Reversible Gates and Testability of One Dimensional Arrays of Molecular QCA Journal of Electronic Testing. 24: 297-311. DOI: 10.1007/S10836-007-5042-2  0.543
2008 Pontarelli S, Ottavi M, Vankamamidi V, Cardarilli GC, Lombardi F, Salsano A. Analysis and Evaluations of Reliability of Reconfigurable FPGAs Journal of Electronic Testing. 24: 105-116. DOI: 10.1007/S10836-007-5040-4  0.336
2008 Ma X, Lombardi F. Substrate Testing on a Multi-Site/Multi-Probe ATE Journal of Electronic Testing. 24: 193-201. DOI: 10.1007/S10836-007-5038-Y  0.473
2008 Jang B, Kim Y, Lombardi F. Monomer Control for Error Tolerance in DNA Self-Assembly Journal of Electronic Testing. 24: 271-284. DOI: 10.1007/S10836-007-5016-4  0.45
2008 Hashempour M, Mashreghian Arani Z, Lombardi F. A circuit model for fault tolerance in the reliable assembly of nano-systems Communications in Computer and Information Science. 6: 705-713. DOI: 10.1007/978-3-540-89985-3_86  0.732
2007 Rossi D, Cazeaux JM, Metra C, Lombardi F. Modeling Crosstalk Effects in CNT Bus Architectures Ieee Transactions On Nanotechnology. 6: 133-145. DOI: 10.1109/Tnano.2007.891814  0.362
2007 Hashempour H, Lombardi F, Necoechea W, Mehta R, Alton T. An Integrated Environment for Design Verification of ATE Systems Ieee Transactions On Instrumentation and Measurement. 56: 1734-1743. DOI: 10.1109/Tim.2007.895611  0.35
2007 Zhang S, Choi M, Park N, Lombardi F. Cost-Driven Optimization of Coverage of Combined Built-In Self-Test/Automated Test Equipment Testing Ieee Transactions On Instrumentation and Measurement. 56: 1094-1100. DOI: 10.1109/Tim.2007.894798  0.347
2007 Lombardi F, Lombardi F, Lombardi F, Lombardi F, Metra C, Metra C, Metra C, Metra C. Guest Editors' Introduction: The State of the Art in Nanoscale CAD Ieee Design & Test of Computers. 24: 302-303. DOI: 10.1109/Mdt.2007.103  0.322
2007 Hashempour M, Arani ZM, Lombardi F. Error tolerance of DNA self-healing assemblies by puncturing Proceedings - Ieee International Symposium On Defect and Fault Tolerance in Vlsi Systems. 400-408. DOI: 10.1109/DFT.2007.8  0.728
2007 Hosseinabady M, Lotfi-Kamran P, Lombardi F, Navabi Z. Low overhead DFT using CDFG by modifying controller Iet Computers and Digital Techniques. 1: 322-333. DOI: 10.1049/Iet-Cdt:20050133  0.315
2007 Huang J, Momenzadeh M, Lombardi F. Design of sequential circuits by quantum-dot cellular automata Microelectronics Journal. 38: 525-537. DOI: 10.1016/J.Mejo.2007.03.013  0.357
2007 Bhanja S, Ottavi M, Lombardi F, Pontarelli S. QCA circuits for robust coplanar crossing Journal of Electronic Testing: Theory and Applications (Jetta). 23: 193-210. DOI: 10.1007/S10836-006-0551-Y  0.338
2007 Huang J, Momenzadeh M, Lombardi F. On the Tolerance to Manufacturing Defects in Molecular QCA Tiles for Processing-by-wire Journal of Electronic Testing. 23: 163-174. DOI: 10.1007/S10836-006-0548-6  0.346
2006 Ottavi M, Schiano L, Lombardi F, Tougaw D. HDLQ Acm Journal On Emerging Technologies in Computing Systems. 2: 243-261. DOI: 10.1145/1216396.1216397  0.373
2005 Huang J, Tahoori MB, Lombardi F. A probabilistic analysis of fault tolerance for switch block array in FPGAs International Journal of Embedded Systems. 1: 250. DOI: 10.1504/Ijes.2005.009954  0.359
2005 Huang J, Momenzadeh M, Schiano L, Ottavi M, Lombardi F. Tile-based QCA design using majority-like logic primitives Acm Journal On Emerging Technologies in Computing Systems. 1: 163-185. DOI: 10.1145/1116696.1116697  0.362
2005 Huang J, Tahoori MB, Lombardi F. Fault tolerance of switch blocks and switch block arrays in FPGA Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 13: 794-807. DOI: 10.1109/Tvlsi.2005.850090  0.386
2005 Wang X, Ottavi M, Meyer F, Lombardi F. Estimating the Manufacturing Yield of Compiler-Based Embedded SRAMs Ieee Transactions On Semiconductor Manufacturing. 18: 412-421. DOI: 10.1109/Tsm.2005.852108  0.382
2005 Vankamamidi V, Ottavi M, Lombardi F. A Line-Based Parallel Memory for QCA Implementation Ieee Transactions On Nanotechnology. 4: 690-698. DOI: 10.1109/Tnano.2005.858589  0.341
2005 Hashempour H, Meyer F, Lombardi F. Analysis and Evaluation of Multisite Testing for VLSI Ieee Transactions On Instrumentation and Measurement. 54: 1770-1778. DOI: 10.1109/Tim.2005.855099  0.333
2005 Hashempour H, Schiano L, Lombardi F. Evaluation, Analysis, and Enhancement of Error Resilience for Reliable Compression of VLSI Test Data Ieee Transactions On Instrumentation and Measurement. 54: 1761-1769. DOI: 10.1109/Tim.2005.855097  0.375
2005 Bahar RI, Tahoori MB, Shukla SK, Lombardi F. Guest editor's introduction: Challenges for reliable design at the nanoscale Ieee Design and Test of Computers. 22: 295-297. DOI: 10.1109/Mdt.2005.84  0.31
2005 Cardarilli GC, Lombardi F, Ottavi M, Pontarelli S, Re M, Salsano A. A Comparative Evaluation of Designs for Reliable Memory Systems Journal of Electronic Testing. 21: 429-444. DOI: 10.1007/S10836-005-0975-9  0.404
2004 Tahoori MB, Huang J, Momenzadeh M, Lombardi F. Testing of quantum cellular automata Ieee Transactions On Nanotechnology. 3: 432-442. DOI: 10.1109/Tnano.2004.834169  0.381
2004 Hashempour H, Meyer F, Lombardi F. Analysis and Measurement of Fault Coverage in a Combined ATE and BIST Environment Ieee Transactions On Instrumentation and Measurement. 53: 300-307. DOI: 10.1109/Tim.2003.822710  0.387
2004 Karimi F, Navabi Z, Meleis WM, Lombardi F. Using Data Compression in Automatic Test Equipment for System-on-Chip Testing Ieee Transactions On Instrumentation and Measurement. 53: 308-317. DOI: 10.1109/Tim.2003.822703  0.341
2004 Choi M, Park N, Piuri V, Kim Y, Lombardi F. Balanced dual-stage repair for dependable embedded memory cores Journal of Systems Architecture. 50: 281-285. DOI: 10.1016/J.Sysarc.2003.08.004  0.38
2004 Navabi Z, Mirkhani S, Lavasani M, Lombardi F. Using RT level component descriptions for single stuck-at hierarchical fault simulation Journal of Electronic Testing: Theory and Applications (Jetta). 20: 575-589. DOI: 10.1007/S10677-004-4247-Z  0.341
2003 Zhao J, Meyer FJ, Lombardi F, Park N. Maximal diagnosis of interconnects of random access memories Ieee Transactions On Reliability. 52: 423-434. DOI: 10.1109/Tr.2003.821928  0.315
2003 Choi M, Park N, Lombardi F. Modeling and analysis of fault tolerant multistage interconnection networks Ieee Transactions On Instrumentation and Measurement. 52: 1509-1519. DOI: 10.1109/Tim.2003.817906  0.354
2003 Feng W, Meyer FJ, Lombardi F. Adaptive algorithms for maximal diagnosis of wiring interconnects Ieee Transactions On Computers. 52: 1259-1270. DOI: 10.1109/Tc.2003.1234524  0.319
2002 Zhao J, Meyer FJ, Lombardi F. Analyzing and diagnosing interconnect faults in bus-structured systems Ieee Design & Test of Computers. 19: 54-64. DOI: 10.1109/54.980053  0.335
2002 Park N, Meyer F, Lombardi F. Quality-effective repair of multichip module systems Journal of Systems Architecture. 47: 883-900. DOI: 10.1016/S1383-7621(01)00038-8  0.351
2001 Feng W, Karimi F, Lombardi F. Fault detection in a tristate system environment Ieee Micro. 21: 77-85. DOI: 10.1109/40.958701  0.332
2001 Park N, Lombardi F, Piuri V. Testing and evaluating the quality-level of stratified multichip module instrumentation Ieee Transactions On Instrumentation and Measurement. 50: 1615-1624. DOI: 10.1109/19.982955  0.315
2000 Liu T, Huang WK, Meyer FJ, Lombardi F. Testing and testable designs for one-time programmable FPGAs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 19: 1370-1375. DOI: 10.1109/43.892860  0.357
2000 Lombardi F, Puri M, Irrinki S, Zhao J. Testing SRAM-based content addressable memories Ieee Transactions On Computers. 49: 1054-1063. DOI: 10.1109/12.888041  0.347
2000 Huang WK, Meyer FJ, Lombardi F. An approach for detecting multiple faulty FPGA logic blocks Ieee Transactions On Computers. 49: 48-54. DOI: 10.1109/12.822563  0.378
1999 Liu T, Chen X, Meyer F, Lombardi F. Test generation and scheduling for layout-based detection of bridge faults in interconnects Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 7: 48-55. DOI: 10.1109/92.748200  0.351
1999 Chen X-, Huang W-, Park N, Meyer FJ, Lombardi F. Design verification of FPGA implementations Ieee Design & Test of Computers. 16: 66-73. DOI: 10.1109/54.765205  0.344
1999 Chen X, Feng W, Zhao J, Meyer FJ, Lombardi F. Reconfiguring one-time programmable FPGAs Ieee Micro. 19: 53-63. DOI: 10.1109/40.809378  0.362
1999 Kim J, Kim S, Lombardi F. Fault-tolerant rank order filtering for image enhancement Ieee Transactions On Consumer Electronics. 45: 436-442. DOI: 10.1109/30.793429  0.353
1999 Zhao J, Meyer FJ, Lombardi F. Journal of Electronic Testing. 15: 157-171. DOI: 10.1023/A:1008396604722  0.323
1998 Chen XT, Meyer FJ, Lombardi F. Structural diagnosis of interconnects by coloring Acm Transactions On Design Automation of Electronic Systems (Todaes). 3: 249-271. DOI: 10.1145/290833.290848  0.351
1998 Huang WK, Meyer FJ, Chen X, Lombardi F. Testing configurable LUT-based FPGA's Ieee Transactions On Very Large Scale Integration Systems. 6: 276-283. DOI: 10.1109/92.678888  0.359
1998 Zhao L, Walker DMH, Lombardi F. I/sub DDQ/ testing of bridging faults in logic resources of reconfigurable field programmable gate arrays Ieee Transactions On Computers. 47: 1136-1152. DOI: 10.1109/12.729796  0.353
1997 Kari H, Saikkonen H, Park N, Lombardi F. Analysis of repair algorithms for mirrored-disk systems Ieee Transactions On Reliability. 46: 193-200. DOI: 10.1109/24.589946  0.324
1996 Feng C, Bhuyan LN, Lombardi F. Adaptive system-level diagnosis for hypercube multiprocessors Ieee Transactions On Computers. 45: 1157-1170. DOI: 10.1109/12.543709  0.321
1996 Salinas J, Shen Y, Lombardi F. A sweeping line approach to interconnect testing Ieee Transactions On Computers. 45: 917-929. DOI: 10.1109/12.536234  0.372
1996 Buonannoa G, Fummi F, Sciuto D, Lombardi F. FsmTest: Functional test generation for sequential circuits Integration. 20: 303-325. DOI: 10.1016/0167-9260(96)00006-5  0.371
1995 Kim S, Lombardi F. Modeling intermediate tests for fault-tolerant multichip module systems Ieee Transactions On Components, Packaging, and Manufacturing Technology: Part B. 18: 448-455. DOI: 10.1109/96.404102  0.378
1995 Liu T, Lombardi F. Diagnosis of interconnects using a structured walking-1 approach Integration. 19: 181-198. DOI: 10.1016/0167-9260(95)00010-1  0.36
1993 Lin H, Lombardi F, Lu M. On the optimal reconfiguration of multipipeline arrays in the presence of faulty processing and switching elements Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 1: 76-79. DOI: 10.1109/92.219910  0.336
1993 Buonanno G, Lombardi F, Sciuto D, Shen Y. Fault detection in TFCMOS/DFCMOS combinational gates Integration. 15: 201-227. DOI: 10.1016/0167-9260(93)90052-E  0.33
1993 Feng C, Muzio JC, Lombardi F. On the testability of array structures for FFT computation Journal of Electronic Testing. 4: 215-224. DOI: 10.1007/Bf00971971  0.383
1992 Lombardi F, Muzio JC. Concurrent Error Detection and Fault Location in an FFT Architecture Ieee Journal of Solid-State Circuits. 27: 728-736. DOI: 10.1109/4.133159  0.424
1992 Lombardi F, Shen Y. Evaluation and improvement of fault coverage of conformance testing by UIO sequences Ieee Transactions On Communications. 40: 1288-1293. DOI: 10.1109/26.156632  0.331
1992 Lombardi F, Feng C, Huang W. Detection and location of multiple faults in baseline interconnection networks Ieee Transactions On Computers. 41: 1340-1344. DOI: 10.1109/12.166613  0.315
1992 Salinas J, Lombardi F. A data path approach for testing microprocessors with a fault bound: the MC68000 case Microprocessors and Microsystems. 16: 529-539. DOI: 10.1016/0141-9331(92)90082-5  0.353
1992 Lombardi F, Sciuto D. Constant testability of combinational cellular tree structures Journal of Electronic Testing. 3: 139-148. DOI: 10.1007/Bf00137251  0.305
1991 Buonanno G, Lombardi F, Sciuto D, Shen Y. Design for testability techniques for CMOS combinational gates Ieee Transactions On Instrumentation and Measurement. 40: 703-708. DOI: 10.1109/19.85338  0.362
1991 Buonanno G, Lombardi F, Sciuto D, Sken Y. Multiple stuck-at faults detection in CMOS combinational gates Microprocessing and Microprogramming. 32: 775-782. DOI: 10.1016/0165-6074(91)90436-W  0.359
1990 Huang WK, Shen Y, Lombardi F. New approaches for the repairs of memories with redundancy by row/column deletion for yield enhancement Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 9: 323-328. DOI: 10.1109/43.46807  0.334
1990 Nuang W, Lombardi F. On the constant diagnosability of baseline interconnection networks Ieee Transactions On Computers. 39: 1458-1458. DOI: 10.1109/12.61073  0.306
1990 Lombardi F, Huang W. Fault detection and design complexity in C-testable VLSI arrays Ieee Transactions On Computers. 39: 1477-1481. DOI: 10.1109/12.61070  0.348
1990 SHEN Y, LOMBARDI F. Fault-tolerant tree architecture with improved reconfiguration capabilities International Journal of Electronics. 69: 723-746. DOI: 10.1080/00207219008920361  0.399
1989 Lombardi F, Sami M, Stefanelli R. Reconfiguration of VLSI arrays by covering Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 8: 952-965. DOI: 10.1109/43.35547  0.329
1989 Lombardi F. On a new class of C-testable systolic arrays Integration. 8: 269-283. DOI: 10.1016/0167-9260(89)90020-5  0.329
1989 Sciuto D, Lombardi F. Functional testing and verification of array systems Microprocessors and Microsystems. 13: 403-412. DOI: 10.1016/0141-9331(89)90049-5  0.366
1988 Lombardi F, Sciuto D, Stefanelli R. An algorithm for functional reconfiguration of fixed-size arrays Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 7: 1114-1118. DOI: 10.1109/43.7810  0.313
1988 Huang W, Lombardi F. On an improved design approach for C-testable orthogonal iterative arrays Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 7: 609-615. DOI: 10.1109/43.3199  0.303
1988 Sciuto D, Lombardi F. On functional testing of array processors Ieee Transactions On Computers. 37: 1480-1484. DOI: 10.1109/12.8724  0.373
1988 LOMBARDI F. A fault-counting algorithm for repairing redundant memories International Journal of Electronics. 64: 869-884. DOI: 10.1080/00207218808962861  0.343
1988 HUANG W, LOMBARDI F. Invited Paper A C-testability approach for two dimensional iterative arrays† International Journal of Electronics. 64: 179-197. DOI: 10.1080/00207218808962794  0.308
1988 Lombardi F. Reconfiguration of hexagonal arrays by diagonal deletion Integration. 6: 263-290. DOI: 10.1016/0167-9260(88)90003-X  0.35
1988 Huang W, Lombardi F. A low complexity approach for fault detection in C-testable orthogonal VLSI arrays Microprocessing and Microprogramming. 22: 277-299. DOI: 10.1016/0165-6074(88)90321-3  0.336
1987 Wey C, Lombardi F. On the Repair of Redundant RAM's Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 6: 222-231. DOI: 10.1109/Tcad.1987.1270266  0.379
1987 Wey C, Vai M, Lombardi F. On the design of a redundant programmable logic array (RPLA) Ieee Journal of Solid-State Circuits. 22: 114-117. DOI: 10.1109/Jssc.1987.1052682  0.343
1987 LOMBARDI F, WEY C. Invited paper. Algorithms for functional testing of digital systems† International Journal of Electronics. 62: 707-732. DOI: 10.1080/00207218708921023  0.352
1987 Kovaleski A, Ratheal S, Lombardi F. An architecture and an interconnection scheme for time-sliced buses Journal of Parallel and Distributed Computing. 4: 209-229. DOI: 10.1016/0743-7315(87)90005-0  0.309
1986 Lombardi F. Comparison-based diagnosis with faulty comparators Electronics Letters. 22: 1158. DOI: 10.1049/El:19860793  0.329
1986 Lombardi F. Diagnosis by comparison with faulty comparators Microprocessing and Microprogramming. 18: 271-274. DOI: 10.1016/0165-6074(86)90055-4  0.34
1985 Lombardi F. Fault detection and identification for reliable large-scale computing Electronics Letters. 21: 50. DOI: 10.1049/El:19850035  0.322
1985 Lombardi F. Diagnosability for fault tolerant parallel systems Microprocessing and Microprogramming. 16: 7-15. DOI: 10.1016/0165-6074(85)90095-X  0.322
1984 Lombardi F. Investigation and design of a controller of an asynchronous system for fault-tolerant aircraft control using hybrid voting techniques Software & Microsystems. 3: 11-18. DOI: 10.1049/Sm:19840003  0.338
1984 Lombardi F. Reconfiguration in microprocessor schemes Microprocessing and Microprogramming. 13: 315-323. DOI: 10.1016/0165-6074(84)90038-3  0.337
1983 Lombardi F. Parallel/series dependency and equivalence in generalized Markov's chains Microelectronics Reliability. 23: 501-507. DOI: 10.1016/0026-2714(83)91179-4  0.312
1983 Lombardi F, Ratheal S. Analysis of series deviance in a parallel state transition diagram and applications to fault tolerant computing Microelectronics Reliability. 23: 963-980. DOI: 10.1016/0026-2714(83)91021-1  0.316
1982 Lombardi F, Obac Roda V. Software implemented fault tolerance: A methodology Microelectronics Reliability. 22: 873-886. DOI: 10.1016/S0026-2714(82)80199-6  0.357
1982 Lombardi F. Microcomputer real time software reliability and fault recovery Microelectronics Reliability. 22: 693-697. DOI: 10.1016/S0026-2714(82)80183-2  0.321
1982 Lombardi F. Availability modelling of ring microcomputer systems Microelectronics Reliability. 22: 295-308. DOI: 10.1016/0026-2714(82)90187-1  0.33
1982 Islam M, Lombardi F. Estimation of total errors in software Microelectronics Reliability. 22: 281-285. DOI: 10.1016/0026-2714(82)90185-8  0.332
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