| Year |
Citation |
Score |
| 2008 |
Choi JW, Apewokin S, Valentine BE, Wills DS, Wills LM. Edge noise removal in multimodal background modeling techniques Proceedings of Spie - the International Society For Optical Engineering. 6813. DOI: 10.1117/12.766829 |
0.304 |
|
| 2008 |
Taha TM, Wills DS. An instruction throughput model of superscalar processors Ieee Transactions On Computers. 57: 389-403. DOI: 10.1109/TC.2007.70817 |
0.604 |
|
| 2005 |
Sassone PG, Wills DS. Scaling up the Atlas chip-multiprocessor Ieee Transactions On Computers. 54: 82-87. DOI: 10.1109/TC.2005.12 |
0.315 |
|
| 2005 |
Kim H, Wills DS, Wills LM. Technology-based architectural analysis of operand bypass networks for efficient operand transport Proceedings - 19th Ieee International Parallel and Distributed Processing Symposium, Ipdps 2005. 2005. DOI: 10.1109/IPDPS.2005.423 |
0.341 |
|
| 2005 |
Robinson WH, Wills DS. Efficiency analysis for a mixed-signal focal plane processing architecture Journal of Vlsi Signal Processing Systems For Signal, Image, and Video Technology. 41: 65-80. DOI: 10.1007/s11265-005-6251-5 |
0.3 |
|
| 2005 |
Kim J, Wills DS, Wills LM. Implementing and evaluating color-aware instruction set for low-memory, embedded video processing in data parallel architectures Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 3824: 4-16. |
0.348 |
|
| 2004 |
Kim J, Wills DS. Combining the quantized color instruction set and loop unrolling on portable video processing systems Proceedings of Spie - the International Society For Optical Engineering. 5309: 80-91. DOI: 10.1117/12.527107 |
0.313 |
|
| 2004 |
Gentile A, Wills DS. Portable video supercomputing Ieee Transactions On Computers. 53: 960-973. DOI: 10.1109/TC.2004.48 |
0.404 |
|
| 2003 |
Robinson WH, Wills DS. Analysis of area-time efficiency for an integrated focal plane architecture Proceedings of Spie - the International Society For Optical Engineering. 5022: 272-283. DOI: 10.1117/12.476615 |
0.332 |
|
| 2002 |
Pant MD, Pant P, Wills DS. On-chip decoupling capacitor optimization using architecture level prediction Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 10: 319-326. DOI: 10.1109/TVLSI.2002.1043335 |
0.591 |
|
| 2002 |
Nugent S, Wills DS, Meindl JD. A hierarchical block-based modeling methodology for SoC in genesys Proceedings of the Annual Ieee International Asic Conference and Exhibit. 2002: 239-243. DOI: 10.1109/ASIC.2002.1158063 |
0.388 |
|
| 2002 |
Robinson WH, Triplett GE, Wills DS. Component modeling for an integrated digital pixel Conference Proceedings - Lasers and Electro-Optics Society Annual Meeting-Leos. 1: 37-38. |
0.388 |
|
| 2001 |
Gentile A, Wills DS. Impact of pixel per processor ratio on embedded SIMD architectures Proceedings - 11th International Conference On Image Analysis and Processing, Iciap 2001. 204-208. DOI: 10.1109/ICIAP.2001.957009 |
0.374 |
|
| 2001 |
Robinson WH, Wills DS. Cost modeling for early image processing applications Proceedings - 2nd International Workshop On Digital and Computational Video, Dcv 2001. 29-34. DOI: 10.1109/DCV.2001.929939 |
0.329 |
|
| 2001 |
Codrescu L, Wills DS, Meindl J. Architecture of the atlas chip-multiprocessor: dynamically parallelizing irregular applications Ieee Transactions On Computers. 50: 67-82. DOI: 10.1109/12.902753 |
0.345 |
|
| 2000 |
Chai SM, Taha TM, Wills DS, Meindl JD. Heterogeneous architecture models for interconnect-motivated system design Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 8: 660-670. DOI: 10.1109/92.902260 |
0.607 |
|
| 2000 |
Pant MD, Pant P, Wills DS. On-chip decoupling capacitor optimization using architectural level prediction Midwest Symposium On Circuits and Systems. 2: 772-775. |
0.591 |
|
| 1998 |
Lacy WS, Cruz-Rivera JL, Wills DS. The offset cube: A three-dimensional multicomputer network topology using through-wafer optics Ieee Transactions On Parallel and Distributed Systems. 9: 893-908. DOI: 10.1109/71.722222 |
0.318 |
|
| 1998 |
May P, Chai SM, Wills DS. HiPER-P: An efficient, high-performance router for multicomputer interconnection networks Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 1417: 103-116. |
0.315 |
|
| 1997 |
Garg V, Stogner DJ, Ulmer C, Schimmel DE, Dislis C, Yalamanchili S, Wills DS. Early analysis of cost/performance trade-offs in MGM systems Ieee Transactions On Components Packaging and Manufacturing Technology Part B. 20: 308-318. DOI: 10.1109/96.618231 |
0.381 |
|
| 1997 |
Wills DS, Cat HH, Cruz-Rivera J, Lacy WS, Baker JM, Eble JC, López-Lagunas A, Hopper M. High-throughput, low-memory applications on the Pica architecture Ieee Transactions On Parallel and Distributed Systems. 8: 1055-1067. DOI: 10.1109/71.629488 |
0.326 |
|
| 1996 |
Wills DS, Baker JM, Cat HH, Chai SM, Codrescu L, Cruz-Rivera J, Eble JC, Gentile A, Hopper MA, Lacy WS, Lôpez-Lagunas A, May P, Smith S, Taha T. Processing architectures for smart pixel systems Ieee Journal On Selected Topics in Quantum Electronics. 2: 24-33. DOI: 10.1109/2944.541872 |
0.532 |
|
| 1995 |
May P, Wilkinson ST, Jokerst NM, Wills DS, Lee M, Vendier O, Bond SW, Hou Z, Dagnall G, Brooke MA, Brown A. Design issues for through-wafer optoelectronic multicomputer interconnects International Conference On Massively Parallel Processing Using Optical Interconnections (Mppoi), Proceedings. 8-15. |
0.323 |
|
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