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Ibrahim N. Hajj - Publications

Affiliations: 
University of Illinois, Urbana-Champaign, Urbana-Champaign, IL 
Area:
Electronics and Electrical Engineering, Computer Science
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62 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2016 Kuh A, Kang SMS, Hajj IN. Introduction to IEEE CASM Special Issue [From the Guest Editors] Ieee Circuits and Systems Magazine. 16: 4-5. DOI: 10.1109/Mcas.2016.2550224  0.37
2016 Hajj IN. Circuit Theory in Circuit Simulation Ieee Circuits and Systems Magazine. 16: 6-10. DOI: 10.1109/Mcas.2016.2549945  0.403
2015 Hajj IN. On device modeling for circuit simulation with application to carbon-nanotube and graphene nano-ribbon field-effect transistors Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 34: 495-499. DOI: 10.1109/Tcad.2014.2387864  0.348
2012 Hajj IN. Extended nodal analysis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 89-100. DOI: 10.1109/Tcad.2011.2167330  0.426
2004 Becer MR, Blaauw D, Algor I, Panda R, Oh C, Zolotov V, Hajj IN. Postroute gate sizing for crosstalk noise reduction Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 23: 1670-1677. DOI: 10.1109/TCAD.2004.836736  0.81
2003 Becer MR, Blaauw D, Algor I, Panda R, Oh C, Zolotov V, Hajj IN. Post-route gate sizing for crosstalk noise reduction Proceedings - Design Automation Conference. 954-957. DOI: 10.1109/Tcad.2004.836736  0.807
2002 Saxena V, Najm FN, Hajj IN. Estimation of state line statistics in sequential circuits Acm Transactions On Design Automation of Electronic Systems. 7: 455-473. DOI: 10.1145/567270.567275  0.489
2002 Ramprasad S, Hajj IN, Najm FN. A technique for improving dual-output domino logic Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 10: 508-511. DOI: 10.1109/Tvlsi.2002.800521  0.43
2002 Becer MR, Blaauw D, Hajj IN. Early Probabilistic Noise Estimation for Capacitively Coupled Interconnects International Workshop On System Level Interconnect Prediction. 77-83. DOI: 10.1109/TCAD.2002.807892  0.81
2002 Becer MR, Blaauw D, Hajj IN. Early Probabilistic Noise Estimation for Capacitively Coupled Interconnects International Workshop On System Level Interconnect Prediction. 77-83. DOI: 10.1109/Tcad.2002.807892  0.806
2002 Becer MR, Blaauw D, Panda R, Hajj IN. Pre-route noise estimation in deep submicron integrated circuits Proceedings - International Symposium On Quality Electronic Design, Isqed. 2002: 413-418. DOI: 10.1109/ISQED.2002.996781  0.814
2002 Bai G, Hajj IN. Simultaneous switching noise and resonance analysis of on-chip power distribution network Proceedings - International Symposium On Quality Electronic Design, Isqed. 2002: 163-168. DOI: 10.1109/ISQED.2002.996723  0.621
2002 Becer MR, Blaauw D, Zolotov V, Panda R, Hajj IN. Analysis of noise avoidance techniques in DSM interconnects using a complete crosstalk noise model Proceedings -Design, Automation and Test in Europe, Date. 456-463. DOI: 10.1109/DATE.2002.998313  0.8
2001 Bobba S, Hajj IN. Input vector generation for maximum intrinsic decoupling capacitance of VLSI circuits Proceedings - Ieee International Symposium On Circuits and Systems. 5: 195-198. DOI: 10.1109ISCAS.2001.922018  0.695
2001 Bai G, Bobba S, Hajj IN. RC power bus maximum voltage drop in digital VLSI circuits Proceedings - International Symposium On Quality Electronic Design, Isqed. 2001: 205-210. DOI: 10.1109/ISQED.2001.915228  0.717
2001 Becer MR, Blaauw D, Sirichotiyakul S, Levy R, Oh C, Zolotov V, Zuo J, Hajj IN. A global driver sizing tool for functional crosstalk noise avoidance Proceedings - International Symposium On Quality Electronic Design, Isqed. 2001: 158-163. DOI: 10.1109/ISQED.2001.915221  0.806
2001 Lu N, Hajj IN. A fast coupling aware delay estimation scheme based on simplified circuit model Proceedings - International Symposium On Quality Electronic Design, Isqed. 2001: 133-138. DOI: 10.1109/ISQED.2001.915217  0.538
2001 Bai G, Bobba S, Hajj IN. Maximum power supply noise estimation in VLSI circuits using multimodal genetic algorithms Proceedings of the Ieee International Conference On Electronics, Circuits, and Systems. 3: 1437-1440.  0.732
2001 Bobba S, Hajj IN. Maximum voltage variation in the power distribution network of VLSI circuits with RLC models Proceedings of the International Symposium On Low Power Electronics and Design, Digest of Technical Papers. 376-381.  0.687
2001 Bai G, Bobba S, Hajj IN. Static timing analysis including power supply noise effect on propagation delay in VLSI circuits Proceedings - Design Automation Conference. 295-300.  0.766
2000 Bai G, Bobba S, Hajj IN. Power bus maximum voltage drop in digital VLSI circuits Proceedings - International Symposium On Quality Electronic Design, Isqed. 2000: 263-268. DOI: 10.1109/ISQED.2000.838881  0.711
2000 Lu N, Hajj IN. A hierarchical based approach for coupling aware delay analysis of combinational logic blocks Proceedings of the Ieee International Conference On Electronics, Circuits, and Systems. 2: 1012-1015. DOI: 10.1109/ICECS.2000.913047  0.603
2000 Becer M, Hajj IN. An analytical model for delay and crosstalk estimation in interconnects under general switching conditions Proceedings of the Ieee International Conference On Electronics, Circuits, and Systems. 2: 831-834. DOI: 10.1109/ICECS.2000.913005  0.348
2000 Bellas N, Hajj IN, Polychronopoulos CD, Stamoulis G. Architectural and compiler techniques for energy reduction in high-performance microprocessors Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 8: 317-326. DOI: 10.1109/92.845897  0.356
2000 Bai G, Bobba S, Hajj IN. Simulation and optimization of the power distribution network in VLSI circuits Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 481-486.  0.683
2000 Bobba S, Hajj IN. Current-mode threshold logic gates Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 235-240.  0.696
2000 Bobba S, Hajj IN. Peak current estimation for digital filters Icassp, Ieee International Conference On Acoustics, Speech and Signal Processing - Proceedings. 6: 3251-3254.  0.662
2000 Bobba S, Hajj IN. High-performance bidirectional repeaters Proceedings of the Ieee Great Lakes Symposium On Vlsi. 53-58.  0.656
1999 Ramprasad S, Shanbhag NR, Hajj IN. Information-theoretic bounds on average signal transition activity Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 7: 359-368. DOI: 10.1109/92.784097  0.302
1999 Ramprasad S, Shanbhag NR, Hajj IN. A coding framework for low-power address and data busses Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 7: 212-221. DOI: 10.1109/92.766748  0.302
1999 Veneris A, Hajj IN. Design error diagnosis and correction via test vector simulation Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 18: 1803-1816. DOI: 10.1109/43.811329  0.375
1999 Bobba S, Hajj IN, Shanbhag NR. Analytical expressions for power dissipation of macro-blocks in DSP architectures Proceedings of the Ieee International Conference On Vlsi Design. 358-363.  0.669
1998 Bobba S, Hajj IN. Maximum current estimation in programmable logic arrays Proceedings of the Ieee Great Lakes Symposium On Vlsi. 301-306. DOI: 10.1109/GLSV.1998.665276  0.706
1998 Bobba S, Hajj IN, Shanbhag NR. Analytical expressions for average bit statistics of signal lines in DSP architectures Proceedings - Ieee International Symposium On Circuits and Systems. 6: 33-36.  0.677
1998 Bobba S, Hajj IN. Estimation of maximum current envelope for power bus analysis and design Proceedings of the International Symposium On Physical Design. 141-146.  0.705
1997 Chung PY, Hajj IN. Diagnosis and correction of multiple logic design errors in digital circuits Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 5: 233-237. DOI: 10.1109/92.585227  0.334
1997 Ramprasad S, Shanbhag NR, Hajj IN. Analytical estimation of signal transition activity from word-level statistics Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 16: 718-733. DOI: 10.1109/43.644033  0.322
1997 Bobba S, Hajj IN. Estimation of maximum switching activity in digital VLSI circuits Midwest Symposium On Circuits and Systems. 2: 1130-1133.  0.713
1996 Li PC, Hajj IN. Computeraided redesign of vlsi circuits for hotcarrier reliability Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 15: 453464. DOI: 10.1109/43.506133  0.477
1995 Kriplani H, Najm FN, Hajj IN. Pattern Independent Maximum Current Estimation in Power and Ground Buses of CMOS VLSI Circuits: Algorithms, Signal Correlations, and Their Resolution Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 14: 998-1012. DOI: 10.1109/43.402499  0.496
1995 Chuang W, Sapatnekar SS, Hajj IN. Timing and Area Optimization for Standard-Cell VLSI Circuit Design Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 14: 308-320. DOI: 10.1109/43.365122  0.438
1994 Chung P, Wang Y, Hajj IN. Logic design error diagnosis and correction Ieee Transactions On Very Large Scale Integration Systems. 2: 320-332. DOI: 10.1109/92.311641  0.354
1994 Stamoulis GI, Hajj IN, Li PC. A Probabilistic Timing Approach to Hot-Carrier Effect Estimation Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 13: 1223-1234. DOI: 10.1109/43.317465  0.35
1993 Yang AT, Chang YH, Saab DG, Hajj IN. Switch-Level Timing Simulation of Bipolar ECL Circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 12: 516-530. DOI: 10.1109/43.229735  0.482
1991 Najm FN, Yang P, Hajj IN. An Extension of Probabilistic Simulation for Reliability Analysis of CMOS VLSI Circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 10: 1372-1381. DOI: 10.1109/43.97616  0.497
1991 Hajj IN, Rao VB, Iimura R, Cha H, Burch R. A system for electromigration analysis in VLSI metal patterns Proceedings of the Custom Integrated Circuits Conference.  0.344
1990 Najm FN, Hajj IN. The Complexity of Fault Detection in MOS VLSI Circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 9: 995-1001. DOI: 10.1109/43.59075  0.346
1990 Najm FN, Burch R, Yang P, Hajj IN. Probabilistic Simulation for Reliability Analysis of CMOS VLSI Circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 9: 439-450. DOI: 10.1109/43.45875  0.479
1989 Saleh RA, Gallivan KA, Chang MC, Hajj IN, Smart D, Trick TN. Parallel Circuit Simulation on Supercomputers Proceedings of the Ieee. 77: 1915-1931. DOI: 10.1109/5.48832  0.312
1989 Wu MY, Hajj IN. Switching Network Logic Approach to Sequential MOS Circuit Design Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 8: 782-794. DOI: 10.1109/43.31535  0.46
1989 Desai MP, Hajj IN. On the convergence of block relaxation methods for circuit simulation Ieee Transactions On Circuits and Systems. 36: 948-958. DOI: 10.1109/31.31330  0.345
1988 Tejayadi O, Hajj IN. DYNAMIC PARTITIONING METHOD FOR PIECEWISE-LINEAR VLSI CIRCUIT SIMULATION International Journal of Circuit Theory and Applications. 16: 457-472. DOI: 10.1002/Cta.4490160409  0.426
1988 Saab DG, Yang AT, Hajj IN. Delay modeling and timing of bipolar digital circuits Proceedings - Design Automation Conference. 288-293.  0.333
1987 Hajj IN, Saab D. Switch-Level Logic Simulation of Digital Bipolar Circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 6: 251-258. DOI: 10.1109/Tcad.1987.1270269  0.44
1987 Tejayadi O, Hajj IN. DYNAMIC PARTITIONING METHOD FOR PIECEWISE-LINEAR MOS DIGITAL CIRCUITS . 102-105.  0.335
1987 Wu MY, Hajj IN. MODIFIED SEQUENTIAL CMOS CIRCUIT DESIGN . 460-463.  0.355
1984 Chia WK, Trick TN, Hajj IN. STABILITY AND CONVERGENCE PROPERTIES OF RELAXATION METHODS FOR HIERARCHICAL SIMULATION OF VLSI CIRCUITS Proceedings - Ieee International Symposium On Circuits and Systems. 2: 848-851.  0.324
1983 Sauer PW, Hajj IN, Pai MA, Trick TN. Computer Methods in Electric Network Analysis Ieee Power Engineering Review. 48. DOI: 10.1109/Mper.1983.5519045  0.346
1979 Hajj IN, Roulston DJ, Bryant PR, Vlach M. Generation and sensitivity of input/output DC plots Computer-Aided Design. 11: 37-39. DOI: 10.1016/0010-4485(79)90009-5  0.375
1978 Roulston DJ, Chamberlain NG, Bryant PR, Hajj IN, Dufond P. Computer-Aided Analysis of Nonlinear JFET Amplifiers from Device Fabrication Data Ieee Journal of Solid-State Circuits. 266-268. DOI: 10.1109/Jssc.1978.1051031  0.342
1977 Hajj IN, Roulston DJ, Bryant PR. Generation of Transient Response of Nonlinear Bipolar Transistor Circuits from Device Fabrication Data Ieee Journal of Solid-State Circuits. 12: 29-38. DOI: 10.1109/Jssc.1977.1050837  0.387
1974 Hajj IN, Roulston DJ, Bryant PR. THREE-TERMINAL PIECEWISE-LINEAR MODELLING APPROACH TO DC ANALYSIS OF TRANSISTOR CIRCUITS International Journal of Circuit Theory and Applications. 2: 133-147. DOI: 10.1016/0010-4485(77)90097-5  0.414
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