Year |
Citation |
Score |
2004 |
Lai L, Rinderknecht T, Cheng WT, Patel JH. Logic BIST using constrained scan cells Proceedings of the Ieee Vlsi Test Symposium. 199-205. |
0.329 |
|
2001 |
Hartanto I, Venkataraman S, Fuchs WK, Rudnick EM, Patel JH, Chakravarty S. Diagnostic simulation of stuck-at faults in sequential circuits using compact lists Acm Transactions On Design Automation of Electronic Systems. 6: 471-489. DOI: 10.1145/502175.502177 |
0.471 |
|
2001 |
Hsu FF, Butler KM, Patel JH. A case study on the implementation of the Illinois Scan Architecture Ieee International Test Conference (Tc). 538-547. |
0.336 |
|
2001 |
Sharma M, Patel JH. Testing of critical paths for delay faults Ieee International Test Conference (Tc). 634-641. |
0.348 |
|
2000 |
Hsiao MS, Rudnick EM, Patel JH. Dynamic state traversal for sequential circuit test generation Acm Transactions On Design Automation of Electronic Systems. 5: 548-565. DOI: 10.1145/348019.348288 |
0.416 |
|
1999 |
Rudnick EM, Patel JH. Efficient techniques for dynamic test sequence compaction Ieee Transactions On Computers. 48: 323-330. DOI: 10.1109/12.754998 |
0.453 |
|
1999 |
Hsiao MS, Rudnick EM, Patel JH. Fast static compaction algorithms for sequential circuit test vectors Ieee Transactions On Computers. 48: 311-322. DOI: 10.1109/12.754997 |
0.452 |
|
1999 |
Hamzaoglu I, Patel JH. New techniques for deterministic test pattern generation Journal of Electronic Testing: Theory and Applications (Jetta). 15: 63-73. DOI: 10.1023/A:1008355411566 |
0.464 |
|
1998 |
Hsiao MS, Rudnick EM, Patel JH. Application of genetically engineered finite-statemachine sequences to sequential circuit ATPG Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 17: 239-254. DOI: 10.1109/43.700722 |
0.424 |
|
1998 |
Hsu FF, Patel JH. High-Level Controllability and Observability Analysis for Test Synthesis Journal of Electronic Testing: Theory and Applications (Jetta). 13: 93-103. DOI: 10.1023/A:1008349603232 |
0.4 |
|
1997 |
Thadikaran P, Chakravarty S, Patel J. Algorithms to compute bridging fault coverage of I DDQ test sets Acm Transactions On Design Automation of Electronic Systems. 2: 281-305. DOI: 10.1145/264995.264999 |
0.411 |
|
1997 |
Rudnick EM, Patel JH, Greenstein GS, Niermann TM. A genetic algorithm framework for test generation Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 16: 1034-1044. DOI: 10.1109/43.658571 |
0.442 |
|
1997 |
Heragu K, Agrawal VD, Bushnell ML, Patel JH. Improving a nonenumerative method to estimate path delay fault coverage Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 16: 759-762. DOI: 10.1109/43.644037 |
0.439 |
|
1997 |
Hsu FF, Patel JH. Design for Testability Using State Distances Journal of Electronic Testing: Theory and Applications (Jetta). 11: 93-100. DOI: 10.1023/A:1008204118797 |
0.372 |
|
1997 |
Graham CR, Rudnick EM, Patel JH. Dynamic fault grouping for PROOFS: a win for large sequential circuits Proceedings of the Ieee International Conference On Vlsi Design. 542-544. |
0.359 |
|
1997 |
Krishnaswamy D, Hsiao MS, Saxena V, Rudnick EM, Patel JH, Banerjee P. Parallel genetic algorithms for simulation-based sequential circuit test generation Proceedings of the Ieee International Conference On Vlsi Design. 475-481. |
0.328 |
|
1997 |
Rudnick EM, Patel JH. Overcoming the serial logic simulation bottleneck in parallel fault simulation Proceedings of the Ieee International Conference On Vlsi Design. 495-501. |
0.384 |
|
1996 |
Cha H, Rudnick EM, Patel JH, Iyer RK, Choi GS. A gate-level simulation environment for alpha-particle-induced transient faults Ieee Transactions On Computers. 45: 1248-1256. DOI: 10.1109/12.544481 |
0.437 |
|
1996 |
Pomeranz I, Reddy SM, Patel JH. On double transition faults as a delay fault model Proceedings of the Ieee Great Lakes Symposium On Vlsi. 282-287. |
0.339 |
|
1995 |
Rudnick EM, Chickermane V, Banerjee P, Patel JH. Sequential Circuit Testability Enhancement Using a Nonscan Approach Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 3: 333-338. DOI: 10.1109/92.386233 |
0.48 |
|
1994 |
Lee J, Patel JH. Architectural Level Test Generation for Microprocessors Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 13: 1288-1300. DOI: 10.1109/43.317464 |
0.325 |
|
1994 |
Rudnick EM, Patel JH, Chickermane V. An Observability Enhancement Approach for Improved Testability and At-Speed Test Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 13: 1051-1056. DOI: 10.1109/43.298041 |
0.479 |
|
1994 |
Chickermane V, Lee J, Patel JH. Addressing Design for Testability at the Architectural Level Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 13: 920-934. DOI: 10.1109/43.293949 |
0.331 |
|
1994 |
Dharchoudhury A, Kang SM, Cha H, Patel JH. Fast timing simulation of transient faults in digital circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 719-722. |
0.374 |
|
1993 |
Choudhary AN, Patel JH, Ahuja N. NETRA: A Hierarchical and Partitionable Architecture for Computer Vision Systems Ieee Transactions On Parallel and Distributed Systems. 4: 1092-1104. DOI: 10.1109/71.246071 |
0.329 |
|
1993 |
Lee J, Patel JH. An architectural level test generator based on nonlinear equation solving Journal of Electronic Testing. 4: 137-150. DOI: 10.1007/Bf00971643 |
0.329 |
|
1992 |
Chickermane V, Lee J, Patel JH. Design for Testability Using Architectural Descriptions Proceedings - International Test Conference. 1992: 752-761. DOI: 10.1109/TEST.1992.527897 |
0.304 |
|
1992 |
Rudnick EM, Fuchs WK, Patel JH. Diagnostic Fault Simulation of Sequential Circuits Proceedings - International Test Conference. 1992: 178-186. DOI: 10.1109/TEST.1992.527818 |
0.365 |
|
1992 |
Lee J, Patel JH. An instruction sequence assembling methodology for testing microprocessors Proceedings - International Test Conference. 1992: 49-58. DOI: 10.1109/TEST.1992.527803 |
0.332 |
|
1992 |
Niermann TM, Roy RK, Patel JH, Abraham JA. Test Compaction for Sequential Circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 11: 260-267. DOI: 10.1109/43.124404 |
0.426 |
|
1992 |
Niermann TM, Cheng WT, Patel JH. PROOFS: A Fast, Memory-Efficient Sequential Circuit Fault Simulator Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 11: 198-207. DOI: 10.1109/43.124398 |
0.498 |
|
1992 |
Mazumder P, Patel JH. An efficient design of embedded memories and their testability analysis using Markov chains Journal of Electronic Testing. 3: 235-250. DOI: 10.1007/Bf00134733 |
0.527 |
|
1991 |
Chatterjee A, Roy RK, Abraham JA, Patel JH. Efficient testing strategies for bit- and digit-serial arrays used in digital signal processors Digital Signal Processing. 1: 231-244. DOI: 10.1016/1051-2004(91)90115-2 |
0.39 |
|
1990 |
Wu KL, Fuchs SWK, Patel JH. Error Recovery in Shared Memory Multiprocessors Using Private Caches Ieee Transactions On Parallel and Distributed Systems. 1: 231-240. DOI: 10.1109/71.80134 |
0.453 |
|
1990 |
Mazumder P, Patel JH, Abraham JA. A Reconfigurable Parallel Signature Analyzer for Concurrent Error Correction in DRAM Ieee Journal of Solid-State Circuits. 25: 866-870. DOI: 10.1109/4.102687 |
0.418 |
|
1990 |
Saleh AM, Serrano JJ, Patel JH. Reliability of Scrubbing Recovery-Techniques for Memory Systems Ieee Transactions On Reliability. 39: 114-122. DOI: 10.1109/24.52622 |
0.395 |
|
1989 |
Chandra SJ, Patel JH. Experimental Evaluation of Testability Measures for Test Generation Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 8: 93-97. DOI: 10.1109/43.21822 |
0.46 |
|
1989 |
Chang MF, Fuchs WK, Patel JH. Diagnosis and Repair of Memory with Coupling Faults Ieee Transactions On Computers. 38: 493-500. DOI: 10.1109/12.21142 |
0.428 |
|
1989 |
Mazumder P, Patel JH. Parallel testing for pattern-sensitive faults in semiconductor random-access memories Ieee Transactions On Computers. 38: 394-407. DOI: 10.1109/12.21126 |
0.475 |
|
1988 |
Saleh AM, Patel JH. Transient-Fault Analysis for Retry Techniques Ieee Transactions On Reliability. 37: 323-330. DOI: 10.1109/24.3763 |
0.342 |
|
1988 |
Laha S, Patel JH, Iyer RK. Accurate Low-Cost Methods for Performance Evaluation of Cache Memory Systems Ieee Transactions On Computers. 37: 1325-1336. DOI: 10.1109/12.8699 |
0.374 |
|
1987 |
Cheng WT, Patel JH. A Minimum Test Set for Multiple Fault Detection in Ripple Carry Adders Ieee Transactions On Computers. 891-895. DOI: 10.1109/TC.1987.1676985 |
0.339 |
|
1987 |
Mazumder P, Patel JH. METHODOLOGIES FOR TESTING EMBEDDED CONTENT ADDRESSABLE MEMORIES Digest of Papers - Ftcs (Fault-Tolerant Computing Symposium). 270-275. DOI: 10.1109/43.3126 |
0.488 |
|
1987 |
Cheng WT, Patel JH. Testing in two-dimensional iterative logic arrays Computers and Mathematics With Applications. 13: 443-454. DOI: 10.1016/0898-1221(87)90074-5 |
0.323 |
|
1987 |
Mazumder P, Patel JH, Fuchs WK. DESIGN AND ALGORITHMS FOR PARALLEL TESTING OF RANDOM ACCESS AND CONTENT ADDRESSABLE MEMORIES Proceedings - Design Automation Conference. 688-694. |
0.362 |
|
1983 |
Abraham JA, Davidson ES, Patel JH. Memory system design for tolerating single event upsets Ieee Transactions On Nuclear Science. 30: 4339-4344. DOI: 10.1109/Tns.1983.4333134 |
0.598 |
|
1983 |
Yeh PCC, Patel JH, Davidson ES. Shared Cache for Multiple-Stream Computer Systems Ieee Transactions On Computers. 38-47. DOI: 10.1109/TC.1983.1676122 |
0.538 |
|
1982 |
Patel JH, Fung LY. Concurrent Error Detection in alu's by Recomputing with Shifted Operands Ieee Transactions On Computers. 589-595. DOI: 10.1109/TC.1982.1676055 |
0.353 |
|
1982 |
Yen DWL, Patel JH, Davidson ES. Memory interference in synchronous multiprocessor systems Ieee Transactions On Computers. 1116-1121. DOI: 10.1109/TC.1982.1675928 |
0.548 |
|
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