| Year |
Citation |
Score |
| 2020 |
Mileiko S, Bunnam T, Xia F, Shafik R, Yakovlev A, Das S. Neural network design for energy-autonomous artificial intelligence applications using temporal encoding. Philosophical Transactions. Series a, Mathematical, Physical, and Engineering Sciences. 378: 20190166. PMID 31865878 DOI: 10.1098/rsta.2019.0166 |
0.322 |
|
| 2020 |
Tenentes V, Das S, Rossi D, Al-Hashimi BM. Run-Time Protection of Multi-Core Processors From Power-Noise Denial-of-Service Attacks Ieee Transactions On Device and Materials Reliability. 20: 319-328. DOI: 10.1109/Tdmr.2020.2994272 |
0.379 |
|
| 2020 |
Fletcher BJ, Das S, Mak T. A Spike-Latency Transceiver With Tunable Pulse Control for Low-Energy Wireless 3-D Integration Ieee Journal of Solid-State Circuits. 55: 2414-2428. DOI: 10.1109/Jssc.2020.2989543 |
0.362 |
|
| 2019 |
Chang K, Das S, Sinha S, Cline B, Yeric G, Lim SK. System-Level Power Delivery Network Analysis and Optimization for Monolithic 3-D ICs Ieee Transactions On Very Large Scale Integration Systems. 27: 888-898. DOI: 10.1109/Tvlsi.2019.2897589 |
0.653 |
|
| 2018 |
Hadjilambrou Z, Das S, Antoniades MA, Sazeides Y. Sensing CPU Voltage Noise Through Electromagnetic Emanations Ieee Computer Architecture Letters. 17: 68-71. DOI: 10.1109/Lca.2017.2766221 |
0.362 |
|
| 2017 |
Karakonstantis G, Nikolopoulos DS, Gizopoulos D, Trancoso P, Sazeides Y, Antonopoulos CD, Venugopal S, Das S. Error-Resilient Server Ecosystems for Edge and Cloud Datacenters Ieee Computer. 50: 78-81. DOI: 10.1109/Mc.2017.4451208 |
0.354 |
|
| 2017 |
Whatmough PN, Das S, Hadjilambrou Z, Bull DM. Power Integrity Analysis of a 28 nm Dual-Core ARM Cortex-A57 Cluster Using an All-Digital Power Delivery Monitor Ieee Journal of Solid-State Circuits. 52: 1643-1654. DOI: 10.1109/Jssc.2017.2669025 |
0.383 |
|
| 2016 |
Aitken R, Chandra V, Cline B, Das S, Pietromonaco D, Shifren L, Sinha S, Yeric G. Predicting future complementary metal–oxide–semiconductor technology – challenges and approaches Iet Computers & Digital Techniques. 10: 315-322. DOI: 10.1049/Iet-Cdt.2015.0210 |
0.64 |
|
| 2015 |
Das S, Bull DM, Whatmough PN. Error-Resilient Design Techniques for Reliable and Dependable Computing Ieee Transactions On Device and Materials Reliability. 15: 24-34. DOI: 10.1109/Tdmr.2015.2389038 |
0.471 |
|
| 2014 |
Das S, Dasika GS, Shivashankar K, Bull D. A 1 GHz hardware loop-accelerator with razor-based dynamic adaptation for energy-efficient operation Ieee Transactions On Circuits and Systems I: Regular Papers. 61: 2290-2298. DOI: 10.1109/Tcsi.2014.2333332 |
0.471 |
|
| 2013 |
Whatmough PN, Das S, Bull DM, Darwazeh I. Circuit-Level Timing Error Tolerance for Low-Power DSP Filters and Transforms Ieee Transactions On Very Large Scale Integration Systems. 21: 989-999. DOI: 10.1109/Tvlsi.2012.2202930 |
0.494 |
|
| 2011 |
Bull D, Das S, Shivashankar K, Dasika GS, Flautner K, Blaauw D. Correction to “A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation” Ieee Journal of Solid-State Circuits. 46: 705-705. DOI: 10.1109/Jssc.2011.2111230 |
0.572 |
|
| 2009 |
Blaauw D, Das S. CPU, heal thyself Ieee Spectrum. 46. DOI: 10.1109/Mspec.2009.5186555 |
0.462 |
|
| 2009 |
Das S, Tokunaga C, Pant S, Ma W-, Kalaiselvan S, Lai K, Bull DM, Blaauw DT. RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance Ieee Journal of Solid-State Circuits. 44: 32-48. DOI: 10.1109/Jssc.2008.2007145 |
0.639 |
|
| 2006 |
Das S, Roberts D, Lee S, Pant S, Blaauw D, Austin T, Flautner K, Mudge T. A self-tuning DVS processor using delay-error detection and correction Ieee Journal of Solid-State Circuits. 41: 792-804. DOI: 10.1109/Jssc.2006.870912 |
0.674 |
|
| 2004 |
Ernst D, Das S, Lee S, Blaauw D, Austin T, Mudge T, Kim NS, Flautner K. Razor: Circuit-level correction of timing errors for low-power operation Ieee Micro. 24: 10-20. DOI: 10.1109/Mm.2004.85 |
0.6 |
|
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