☰

Aviral Shrivastava, Ph.D. - Publications

Affiliations: 
2006 University of California, Irvine, Irvine, CA 
Area:
Computer Science
Tree Info Similar researchers PubMed Report error

46 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2019 Dave S, Kim Y, Avancha S, Lee K, Shrivastava A. dMazeRunner: Executing Perfectly Nested Loops on Dataflow Accelerators Acm Transactions in Embedded Computing Systems. 18: 70. DOI: 10.1145/3358198  0.71
2018 Didehban M, Shrivastava A. A Compiler Technique for Processor-Wide Protection From Soft Errors in Multithreaded Environments Ieee Transactions On Reliability. 67: 249-263. DOI: 10.1109/Tr.2018.2793098  0.477
2017 Mehrabian M, Khayatian M, Shrivastava A, Eidson JC, Derler P, Andrade HA, Li-Baboud Y, Griffor E, Weiss M, Stanton K. Timestamp Temporal Logic (TTL) for Testing the Timing of Cyber-Physical Systems Acm Transactions in Embedded Computing Systems. 16: 169. DOI: 10.1145/3126510  0.338
2017 Kim Y, Broman D, Shrivastava A. WCET-Aware Function-Level Dynamic Code Management on Scratchpad Memory Acm Transactions in Embedded Computing Systems. 16: 112. DOI: 10.1145/3063383  0.411
2017 Ko Y, Jeyapaul R, Kim Y, Lee K, Shrivastava A. Protecting Caches from Soft Errors: A Microarchitect’s Perspective Acm Transactions in Embedded Computing Systems. 16: 93. DOI: 10.1145/3063180  0.649
2016 Didehban M, Shrivastava A. NZDC: A compiler technique for near zero silent data corruption Proceedings - Design Automation Conference. 5. DOI: 10.1145/2897937.2898054  0.366
2016 Cai J, Shrivastava A. Software Coherence Management on Non-coherent Cache Multi-cores Proceedings of the Ieee International Conference On Vlsi Design. 2016: 397-402. DOI: 10.1109/VLSID.2016.70  0.314
2016 Jeyapaul R, Flores R, Avila A, Shrivastava A. Systematic Methodology for the Quantitative Analysis of Pipeline-Register Reliability Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. DOI: 10.1109/Tvlsi.2016.2574642  0.493
2016 Shrivastava A, Sharma SK. Various arbitration algorithm for on-chip(AMBA) shared bus multi-processor SoC 2016 Ieee Students' Conference On Electrical, Electronics and Computer Science, Sceecs 2016. DOI: 10.1109/SCEECS.2016.7509330  0.327
2016 Shrivastava A, Dutt N, Cai J, Shoushtari M, Donyanavard B, Tajik H. Automatic management of Software Programmable Memories in Many-core Architectures Iet Computers & Digital Techniques. 10: 288-298. DOI: 10.1049/Iet-Cdt.2016.0024  0.561
2015 Lu J, Bai K, Shrivastava A. Efficient code assignment techniques for local memory on software managed multicores Acm Transactions On Embedded Computing Systems. 14. DOI: 10.1145/2738039  0.41
2015 Pager J, Jeyapaul R, Shrivastava A. A software scheme for multithreading on CGRAs Acm Transactions On Embedded Computing Systems. 14. DOI: 10.1145/2638558  0.441
2015 Rawat T, Shrivastava A. Enabling multi-threaded applications on hybrid shared memory manycore architectures Proceedings -Design, Automation and Test in Europe, Date. 2015: 742-747.  0.31
2014 Jeyapaul R, Hong F, Rhisheekesan A, Shrivastava A, Lee K. UnSync-CMP: Multicore CMP Architecture for Energy-Efficient Soft-Error Reliability Ieee Transactions On Parallel and Distributed Systems. 25: 254-263. DOI: 10.1109/Tpds.2013.14  0.689
2013 Lee J, Shrivastava A. Software-based register file vulnerability reduction for embedded processors Transactions On Embedded Computing Systems. 13. DOI: 10.1145/2536747.2536760  0.439
2013 Kim Y, Shrivastava A. Memory performance estimation of CUDA programs Transactions On Embedded Computing Systems. 13. DOI: 10.1145/2514641.2514648  0.392
2013 Jeyapaul R, Shrivastava A. Enabling energy efficient reliability in embedded systems through smart cache cleaning Acm Transactions On Design Automation of Electronic Systems. 18. DOI: 10.1145/2505012  0.572
2013 Bai K, Shrivastava A. A software-only scheme for managing heap data on limited local memory(LLM) multicore processors Transactions On Embedded Computing Systems. 13. DOI: 10.1145/2501626.2501632  0.412
2013 Bai K, Shrivastava A. Automatic and efficient heap data management for limited local memory multicore architectures Proceedings -Design, Automation and Test in Europe, Date. 593-598.  0.304
2012 Lee J, Shrivastava A. PICA: Processor idle cycle aggregation for energy-efficient embedded systems Transactions On Embedded Computing Systems. 11. DOI: 10.1145/2220336.2220338  0.459
2012 Hong F, Shrivastava A, Lee J. Return Data Interleaving for Multi-Channel Embedded CMPs Systems Ieee Transactions On Very Large Scale Integration Systems. 20: 1351-1354. DOI: 10.1109/Tvlsi.2011.2157368  0.388
2011 Jeyapaul R, Shrivastava A. Smart cache cleaning: Energy efficient vulnerability reduction in embedded processors Embedded Systems Week 2011, Esweek 2011 - Proceedings of the 14th International Conference On Compilers, Architectures and Synthesis For Embedded Systems, Cases'11. 105-114. DOI: 10.1145/2038698.2038716  0.441
2011 Kim Y, Lee J, Shrivastava A, Paek Y. Memory access optimization in compilation for coarse-grained reconfigurable architectures Acm Transactions On Design Automation of Electronic Systems. 16: 42. DOI: 10.1145/2003695.2003702  0.395
2011 Kim Y, Lee J, Shrivastava A, Yoon JW, Cho D, Paek Y. High Throughput Data Mapping for Coarse-Grained Reconfigurable Architectures Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 30: 1599-1609. DOI: 10.1109/Tcad.2011.2161217  0.427
2011 Lee J, Shrivastava A. Static analysis of register file vulnerability Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 30: 607-616. DOI: 10.1109/Tcad.2010.2095630  0.402
2010 Bai K, Shrivastava A. Heap data management for limited local memory (LLM) multi-core processors Embedded Systems Week 2010 - Proceedings of the 8th Ieee/Acm/Ifip International Conference On Compilers, Architecture and Synthesis For Embedded Systems, Codes+Isss'2010. 317-325. DOI: 10.1145/1878961.1879015  0.307
2010 Lee K, Shrivastava A, Dutt N, Venkatasubramanian N. Partitioning techniques for partially protected caches in resource-constrained embedded systems Acm Transactions On Design Automation of Electronic Systems. 15. DOI: 10.1145/1835420.1835423  0.717
2010 Jeyapaul R, Shrivastava A. B2P2: Bounds Based Procedure Placement for instruction TLB power reduction in embedded systems Proceedings of the 13th International Workshop On Software and Compilers For Embedded Systems, Scopes 2010. DOI: 10.1145/1811212.1811215  0.34
2010 Shrivastava A, Kannan D, Bhardwaj S, Vrudhula S. Reducing functional unit power consumption and its variation using leakage sensors Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 18: 988-997. DOI: 10.1109/Tvlsi.2009.2019082  0.404
2010 Lee J, Shrivastava A. A Compiler-Microarchitecture Hybrid Approach to Soft Error Reduction for Register Files Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 29: 1018-1027. DOI: 10.1109/Tcad.2010.2049050  0.45
2010 Jeyapaul R, Shrivastava A. Code transformations for TLB power reduction International Journal of Parallel Programming. 38: 254-276. DOI: 10.1007/S10766-009-0123-8  0.493
2009 Lee J, Shrivastava A. A compiler optimization to reduce soft errors in register files Acm Sigplan Notices. 44: 41-49. DOI: 10.1145/1542452.1542459  0.346
2009 Lee K, Shrivastava A, Issenin I, Dutt N, Venkatasubramanian N. Partially Protected Caches to Reduce Failures Due to Soft Errors in Multimedia Applications Ieee Transactions On Very Large Scale Integration Systems. 17: 1343-1347. DOI: 10.1109/Tvlsi.2008.2002427  0.668
2009 Yoon JW, Shrivastava A, Park S, Ahn M, Paek Y. A Graph Drawing Based Spatial Mapping Algorithm for Coarse-Grained Reconfigurable Architectures Ieee Transactions On Very Large Scale Integration Systems. 17: 1565-1578. DOI: 10.1109/Tvlsi.2008.2001746  0.341
2009 Shrivastava A, Kannan A, Lee J. A software-only solution to use scratch pads for stack data Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 28: 1719-1727. DOI: 10.1109/Tcad.2009.2030592  0.413
2009 Shrivastava A, Issenin I, Dutt N, Park S, Paek Y. Compiler-in-the-Loop Design Space Exploration Framework for Energy Reduction in Horizontally Partitioned Cache Architectures Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 28: 461-465. DOI: 10.1109/Tcad.2009.2013275  0.673
2009 Lee J, Shrivastava A. Compiler-managed register file protection for energy-efficient soft error reduction Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 618-623. DOI: 10.1109/ASPDAC.2009.4796549  0.332
2009 Lee J, Shrivastava A. A compiler optimization to reduce soft errors in register files Acm Sigplan Notices. 44: 41-49.  0.346
2009 Lee J, Shrivastava A. Static analysis to mitigate soft errors in register files Proceedings -Design, Automation and Test in Europe, Date. 1367-1372.  0.308
2008 Lee J, Shrivastava A. Static analysis of processor stall cycle aggregation Embedded Systems Week 2008 - Proceedings of the 6th Ieee/Acm/Ifip International Conference On Hardware/Software Codesign and System Synthesis, Codes+Isss 2008. 25-30. DOI: 10.1145/1450135.1450143  0.376
2008 Park S, Shrivastava A, Dutt N, Nicolau A, Paek Y, Earlie E. Register File Power Reduction Using Bypass Sensitive Compiler Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 1155-1159. DOI: 10.1109/Tcad.2008.923254  0.555
2008 Mishra P, Shrivastava A. ADL-driven Methodologies for Design Automation of Embedded Processors Processor Description Languages. 13-33. DOI: 10.1016/B978-012374287-2.50005-7  0.349
2007 Shrivastava A, Sanghyun P, Earlie E, Dutt ND, Nicolau A, Yunheung P. Automatic Design Space Exploration of Register Bypasses in Embedded Processors Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 2102-2115. DOI: 10.1109/Tcad.2007.907066  0.463
2006 Shrivastava A, Biswas P, Halambi A, Dutt N, Nicolau A. Compilation framework for code size reduction using reduced bit-width ISAs (rISAs) Acm Transactions On Design Automation of Electronic Systems. 11: 123-146. DOI: 10.1145/1124713.1124722  0.549
2006 Shrivastava A, Earlie E, Dutt N, Nicolau A. Retargetable pipeline hazard detection for partially bypassed processors Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 14: 791-801. DOI: 10.1109/Tvlsi.2006.878468  0.594
2004 Shrivastava A, Dutt N. Energy efficient code generation exploiting reduced Bit-width instruction set architectures (rISA) Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 475-477.  0.586
Show low-probability matches.