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Jongsun Kim, Ph.D. - Publications

Affiliations: 
2006 University of California, Los Angeles, Los Angeles, CA 
Area:
Electronics and Electrical Engineering
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31 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Hwang H, Kim J. A 100 Gb/s Quad-Lane SerDes Receiver with a PI-Based Quarter-Rate All-Digital CDR Electronics. 9: 1113. DOI: 10.3390/Electronics9071113  0.425
2020 Kim J. A wide-range all-digital phase inversion DLL for high-speed DRAMs Analog Integrated Circuits and Signal Processing. 102: 39-51. DOI: 10.1007/S10470-019-01535-6  0.477
2020 Park D, Kim J. A 7-GHz Fast-Lock Two-Step Time-to-Digital Converter-Based All-Digital DLL Circuits Systems and Signal Processing. 39: 1715-1734. DOI: 10.1007/S00034-019-01230-X  0.458
2019 Hwang H, Kim J. A 0.8–3.4 GHz process variation insensitive duty-cycle corrector for high-speed memory I/O links Ieice Electronics Express. 16: 20190505-20190505. DOI: 10.1587/Elex.16.20190505  0.336
2018 Kim J, Shin H. A Low-power 3.52 Gbps SerDes with a MDLL Frequency Multiplier for High-speed On-chip Networks Journal of Semiconductor Technology and Science. 18: 658-666. DOI: 10.5573/Jsts.2018.18.6.658  0.449
2018 Kim J, Han S. A low-power fast-lock DCC with a digital duty-cycle adjuster for LPDDR3 and LPDDR4 DRAMs Ieice Electronics Express. 15: 20180156-20180156. DOI: 10.1587/Elex.15.20180156  0.399
2018 Kim J, Bae B. An anti-harmonic MDLL for phase-aligned on-chip clock multiplication Ieice Electronics Express. 15: 20180042-20180042. DOI: 10.1587/Elex.15.20180042  0.301
2018 Kim J. An anti-boundary switching fine-resolution digital delay-locked loop Analog Integrated Circuits and Signal Processing. 96: 445-454. DOI: 10.1007/S10470-018-1206-5  0.449
2017 Kim J, Bae B. A 2-4 GHz fast-locking frequency multiplying delay-locked loop Ieice Electronics Express. 14: 20161056-20161056. DOI: 10.1587/Elex.13.20161056  0.364
2017 Yoon J, Heo SW, Kim J. A fast-locking harmonic-free digital DLL for DDR3 and DDR4 SDRAMs Ieice Electronics Express. 14: 20161020-20161020. DOI: 10.1587/Elex.13.20161020  0.335
2017 Kim J, Han S. A Fast-Locking All-Digital Multiplying DLL for Fractional-Ratio Dynamic Frequency Scaling Ieee Transactions On Circuits and Systems Ii-Express Briefs. 65: 276-280. DOI: 10.1109/Tcsii.2017.2688369  0.413
2016 Kim J, Han S. A High-Resolution Dual-Loop Digital DLL Journal of Semiconductor Technology and Science. 16: 520-527. DOI: 10.5573/Jsts.2016.16.4.520  0.426
2016 Han S, Lim J, Kim J. An area-efficient multi-phase fractional-ratio clock frequency multiplier Journal of Semiconductor Technology and Science. 16: 143-146. DOI: 10.5573/Jsts.2016.16.1.143  0.407
2015 Lee S, Jeong Y, Song Y, Kim J. A Low-Power Single Chip Li-Ion Battery Protection IC Journal of Semiconductor Technology and Science. 15: 445-453. DOI: 10.5573/Jsts.2015.15.4.445  0.329
2015 Lee D, Kim J. 5 GHz all-digital delay-locked loop for future memory systems beyond double data rate 4 synchronous dynamic random access memory Electronics Letters. 51: 1973-1975. DOI: 10.1049/El.2015.2876  0.463
2014 Ku J, Bae B, Kim J. A 13-Gbps Low-swing Low-power Near-ground Signaling Transceiver Journal of the Institute of Electronics Engineers of Korea. 51: 49-58. DOI: 10.5573/Ieie.2014.51.4.049  0.358
2014 Lee D, Kim J. A CMOS RF Power Detector Using an AGC Loop Journal of the Institute of Electronics Engineers of Korea. 51: 101-106. DOI: 10.5573/Ieie.2014.51.11.101  0.375
2014 Han S, Kim J, Kim J. Programmable fractional-ratio frequency multiplying clock generator Electronics Letters. 50: 163-165. DOI: 10.1049/El.2013.2857  0.406
2013 Park G, Kim H, Kim J. A Reset-Free Anti-Harmonic Programmable MDLL-Based Frequency Multiplier Jsts:Journal of Semiconductor Technology and Science. 13: 459-464. DOI: 10.5573/Jsts.2013.13.5.459  0.403
2013 Han S, Kim J. A 0.5-2.0 GHz Dual-Loop SAR-controlled Duty-Cycle Corrector Using a Mixed Search Algorithm Journal of Semiconductor Technology and Science. 13: 152-156. DOI: 10.5573/Jsts.2013.13.2.152  0.379
2012 Han S, Kim J. A CMOS Duty Cycle Corrector Using Dynamic Frequency Scaling for Coarse and Fine Tuning Adjustment Journal of the Institute of Electronics Engineers of Korea. 49: 142-147. DOI: 10.5573/Ieek.2012.49.10.142  0.386
2012 Byun G, Kim Y, Kim J, Tam S, Chang MF. An Energy-Efficient and High-Speed Mobile Memory I/O Interface Using Simultaneous Bi-Directional Dual (Base+RF)-Band Signaling Ieee Journal of Solid-State Circuits. 47: 117-130. DOI: 10.1109/Jssc.2011.2164709  0.641
2011 Lee K, Kim J. Design of an Integrated High Voltage Pulse Generation circuit for Driving Piezoelectric Printer Heads Journal of the Korean Institute of Illuminating and Electrical Installation Engineers. 25: 80-86. DOI: 10.5207/Jieie.2011.25.2.080  0.374
2011 Kim J, Byun G, Chang MF. A low-overhead and low-power rf transceiver for short-distance on- and off-chip interconnects Ieice Transactions On Electronics. 854-857. DOI: 10.1587/Transele.E94.C.854  0.66
2011 Han S, Kim J. Hybrid duty-cycle corrector circuit with dual feedback loop Electronics Letters. 47: 1311-1313. DOI: 10.1049/El.2011.2710  0.389
2010 Ju H, Kim J. A low-power wideband multi-frequency synthesizer for mobile TV tuner ICs Ieice Electronics Express. 7: 92-97. DOI: 10.1587/Elex.7.92  0.425
2009 Kim J. Area-efficient digitally controlled CMOS feedback delay element with programmable duty cycle Ieice Electronics Express. 6: 193-197. DOI: 10.1587/Elex.6.193  0.37
2008 Kim J, Lai BC, Verbauwhede I. A cost-effective latency-aware memory bus for symmetric multiprocessor systems Ieee Transactions On Computers. 57: 1714-1719. DOI: 10.1109/Tc.2008.96  0.321
2007 Kim J, Verbauwhede I, Chang MCF. Design of an interconnect architecture and signaling technology for parallelism in communication Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 15: 881-893. DOI: 10.1109/Tvlsi.2007.900739  0.366
2005 Chang M-F, Verbauwhede I, Chien C, Xu Z, Kim J, Ko J, Gu Q, Lai B. Advanced RF/baseband interconnect schemes for inter- and intra-ULSI communications Ieee Transactions On Electron Devices. 52: 1271-1285. DOI: 10.1109/Ted.2005.850699  0.357
2005 Kim J, Verbauwhede I, Chang M-F. A 5.6-mW 1-Gb/s/pair pulsed signaling transceiver for a fully AC coupled bus Ieee Journal of Solid-State Circuits. 40: 1331-1340. DOI: 10.1109/Jssc.2005.848030  0.424
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