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Haiqing Nan, Ph.D. - Publications

Affiliations: 
2012 Illinois Institute of Technology, Chicago, IL, United States 
Area:
Electronics and Electrical Engineering
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20 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2015 Choi K, Nan H, Choi W. Advances in Smart and Intelligent Multimedia Platforms for Pervasive Computing Multimedia Tools and Applications. 74: 1537-1539. DOI: 10.1007/S11042-015-2486-8  0.461
2014 Choi KW, Nan H. Editorial for Special Issue on "challenges pervasive network and applications for internet of things" Mobile Networks and Applications. 19: 360-362. DOI: 10.1007/S11036-014-0515-X  0.358
2013 Li L, Choi K, Nan H. Activity-driven fine-grained clock gating and run time power gating integration Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 21: 1540-1544. DOI: 10.1109/Tvlsi.2012.2212732  0.577
2013 Nan H, Choi K. TDDB monitoring and compensation circuit design for deeply scaled CMOS technology Ieee Transactions On Device and Materials Reliability. 13: 18-25. DOI: 10.1109/Tdmr.2011.2167624  0.479
2012 Nan H, Choi K. High performance, low cost, and robust soft error tolerant latch designs for nanoscale CMOS technology Ieee Transactions On Circuits and Systems I: Regular Papers. 59: 1445-1457. DOI: 10.1109/Tcsi.2011.2177135  0.6
2012 Nan H, Li L, Choi K. TDDB-based performance variation of combinational logic in deeply scaled CMOS technology Proceedings - International Symposium On Quality Electronic Design, Isqed. 328-333. DOI: 10.1109/ISQED.2012.6187513  0.353
2012 Nan H, Choi K. Soft error tolerant latch design with low cost for nanoelectronic systems Iscas 2012 - 2012 Ieee International Symposium On Circuits and Systems. 1572-1575. DOI: 10.1109/ISCAS.2012.6271553  0.386
2012 Nan H, Choi K. Low cost and highly reliable hardened latch design for nanoscale CMOS technology Microelectronics Reliability. 52: 1209-1214. DOI: 10.1016/J.Microrel.2012.01.001  0.592
2011 Nan H, Kim KK, Wang W, Choi K. Dynamic Voltage and Frequency Scaling for Power-Constrained Design using Process Voltage and Temperature Sensor Circuits Journal of Information Processing Systems. 7: 93-102. DOI: 10.3745/Jips.2011.7.1.093  0.593
2011 Sriram S, Nan H, Choi K. Low power latch design in near sub-threshold region to improve reliability for soft error Proceedings of the 12th International Symposium On Quality Electronic Design, Isqed 2011. 611-614. DOI: 10.1109/ISQED.2011.5770791  0.424
2011 Li L, Choi K, Nan H. Effective algorithm for integrating clock gating and power gating to reduce dynamic and active leakage power simultaneously Proceedings of the 12th International Symposium On Quality Electronic Design, Isqed 2011. 74-79. DOI: 10.1109/ISQED.2011.5770706  0.305
2011 Nan H, Choi K. Novel radiation hardened latch design considering process, voltage and temperature variations for nanoscale CMOS technology Microelectronics Reliability. 51: 2086-2092. DOI: 10.1016/J.Microrel.2011.07.048  0.618
2010 Nan H, Choi K. Novel ternary logic design based on CNFET 2010 International Soc Design Conference, Isocc 2010. 115-118. DOI: 10.1109/SOCDC.2010.5682960  0.394
2010 Nan H, Choi K. Novel soft error hardening design of nanoscale CMOS latch 2010 International Soc Design Conference, Isocc 2010. 111-114. DOI: 10.1109/SOCDC.2010.5682959  0.38
2010 Sriram S, Nan H, Choi K. Dual loop hardened latch circuit for low power application 2010 International Soc Design Conference, Isocc 2010. 123-126. DOI: 10.1109/SOCDC.2010.5682958  0.396
2010 Kim KK, Nan H, Choi K. Hybrid MOSFET/CNFET based power gating structure Proceedings - Ieee International Soc Conference, Socc 2010. 334-338. DOI: 10.1109/SOCC.2010.5784689  0.354
2010 Kim KK, Nan H, Choi K. Adaptive HCI-aware power gating structure Proceedings of the 11th International Symposium On Quality Electronic Design, Isqed 2010. 219-224. DOI: 10.1109/ISQED.2010.5450418  0.374
2010 Kim KK, Nan H, Choi K. Power gating for ultra-low voltage nanometer ICs Iscas 2010 - 2010 Ieee International Symposium On Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 1472-1475. DOI: 10.1109/ISCAS.2010.5537343  0.381
2009 Kim KK, Nan H, Choi K. Ultralow-voltage power gating structure using low threshold voltage Ieee Transactions On Circuits and Systems Ii: Express Briefs. 56: 926-930. DOI: 10.1109/Tcsii.2009.2035268  0.594
2009 Nan H, Choi K. Inter-hierarchical power analysis methodology to reduce multiple orders of magnitude run-time without compromizing accuracy 2009 International Soc Design Conference, Isocc 2009. 556-559.  0.312
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