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Yijian Chen, Ph.D. - Publications

Affiliations: 
2004 University of California, Berkeley, Berkeley, CA, United States 
Area:
Electronics and Electrical Engineering
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37 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2017 Hong C, Zhou J, Huang J, Wang R, Bai W, Kuo JB, Chen Y. A General and Transformable Model Platform for Emerging Multi-Gate MOSFETs Ieee Electron Device Letters. 38: 1015-1018. DOI: 10.1109/Led.2017.2722227  0.328
2016 Zhou J, Chen Y. A comparative study on the yield performance of via landing and direct stitching processes for 2D pattern connection Proceedings of Spie. 9781. DOI: 10.1117/12.2219336  0.365
2016 Liu H, Hong C, Han T, Zhou J, Chen Y. Structural design, layout analysis and routing strategy for constructing IC standard cells using emerging 3D vertical MOSFETs Proceedings of Spie. 9781: 978103. DOI: 10.1117/12.2219267  0.393
2016 Liu H, Han T, Zhou J, Chen Y. Layout decomposition and synthesis for a modular technology to solve the edge-placement challenges by combining selective etching, direct stitching, and alternating-material self-aligned multiple patterning processes Proceedings of Spie. 9781. DOI: 10.1117/12.2219082  0.46
2016 Han T, Hong C, Cheng Q, Chen Y. Impacts of process variability of alternating-material self-aligned multiple patterning on SRAM circuit performance Proceedings of Spie. 9781. DOI: 10.1117/12.2218992  0.437
2016 Han T, Liu H, Chen Y. A paradigm shift in patterning foundation from frequency multiplication to edge-placement accuracy: a novel processing solution by selective etching and alternating-material self-aligned multiple patterning Proceedings of Spie. 9777: 977718. DOI: 10.1117/12.2218874  0.45
2016 Han T, Liu H, Chen Y. Process development and edge-placement yield modeling of alternating-material self-aligned multiple patterning Journal of Micro-Nanolithography Mems and Moems. 15: 31609-31609. DOI: 10.1117/1.Jmm.15.3.031609  0.444
2016 Hong C, Yang L, Cheng Q, Han T, Kuo JB, Chen Y. A continuous compact model incorporating higher-order correction for junctionless nanowire transistors with arbitrary doping profiles Ieee Transactions On Nanotechnology. 15: 657-665. DOI: 10.1109/Tnano.2016.2570813  0.319
2016 Liu H, Han T, Chen Y. Cut-hole layout decomposition and synthesis to reduce the effect of edge-placement errors Microelectronic Engineering. 155: 107-113. DOI: 10.1016/J.Mee.2016.03.048  0.414
2015 Wang P, Hong C, Cheng Q, Chen Y. A compact model to predict pillar-edge-roughness effects on 3D vertical nanowire MOSFETs using the perturbation method Proceedings of Spie. 9427. DOI: 10.1117/12.2085919  0.34
2015 Zhou J, Liu H, Han T, Chen Y. Breaking through 1D layout limitations and regaining 2D design freedom part II: stitching yield modeling and optimization Proceedings of Spie. 9427: 942714. DOI: 10.1117/12.2085898  0.384
2015 Cheng Q, Chen Y. Statistical modeling of SRAM yield performance and circuit variability Proceedings of Spie. 9427. DOI: 10.1117/12.2085844  0.408
2015 Liu H, Zhou J, Chen Y. Breaking through 1D layout limitations and regaining 2D design freedom Part I: 2D layout decomposition and stitching techniques for hybrid optical and self-aligned multiple patterning Proceedings of Spie. 9427. DOI: 10.1117/12.2085738  0.398
2015 Liu H, Zhou J, Chen Y. Random 2-D layout decomposition and synthesis using self-aligned multiple patterning and stitching techniques Microelectronic Engineering. 141: 188-192. DOI: 10.1016/J.Mee.2015.03.029  0.394
2014 Zhang P, Hong C, Chen Y. A Generalized Edge-Placement Yield Model for the Cut-Hole Patterning Process Proceedings of Spie. 9052. DOI: 10.1117/12.2046437  0.381
2014 You J, Liu H, Chen Y. A layout decomposition algorithm for self-aligned multiple patterning Proceedings of Spie. 9053: 905310. DOI: 10.1117/12.2046390  0.414
2014 Cheng Q, You J, Chen Y. A generalized model to predict fin-width roughness induced FinFET device variability using the boundary perturbation method Proceedings of Spie. 9053. DOI: 10.1117/12.2046221  0.321
2014 Yu J, Xiao W, Kang W, Chen Y. Understanding the critical challenges of self-aligned octuple patterning Proceedings of Spie. 9052. DOI: 10.1117/12.2046094  0.427
2014 Chen Y, Zhou J, You J, Liu H. Benchmarking process integration and layout decomposition of directed self-assembly and self-aligned multiple patterning techniques Proceedings of Spie. 9053. DOI: 10.1117/12.2046085  0.434
2014 Chen Y, Shroff Y. A Frequency Multiplication Technique Based on EUV Near-Field Imaging Proceedings of Spie. 9049. DOI: 10.1117/12.2045880  0.679
2014 Zhang P, Chen Y. Modeling the edge-placement yield of a cut process for self-aligned multiple patterning Microelectronic Engineering. 123: 73-79. DOI: 10.1016/J.Mee.2014.05.025  0.398
2014 Cheng Q, You J, Chen Y. Correlating FinFET device variability to the spatial fluctuation of fin width Microelectronic Engineering. 119: 53-60. DOI: 10.1016/J.Mee.2014.01.021  0.346
2013 Xiao W, Cheng Q, Chen Y. SRAM circuit performance in the presence of process variability of self-aligned multiple patterning Proceedings of Spie. 8684. DOI: 10.1117/12.2011686  0.407
2013 Cheng Q, Kang W, Chen Y. Compact Modeling of Fin-Width Roughness Induced FinFET Device Variability Using the Perturbation Method Proceedings of Spie. 8684. DOI: 10.1117/12.2011551  0.325
2013 Kang W, Chen Y. Process characteristics and layout decomposition of self-aligned sextuple patterning Proceedings of Spie. 8684. DOI: 10.1117/12.2011370  0.367
2013 Kang W, Feng C, Chen Y. Mask strategy and layout decomposition for self-aligned quadruple patterning Proceedings of Spie. 8684. DOI: 10.1117/12.2011261  0.407
2013 Zhang P, Chen Y. Cut-process overlay yield model for self-aligned multiple patterning and a misalignment correction technique based on dry etching Proceedings of Spie. 8685. DOI: 10.1117/12.2010584  0.422
2013 Chen Y, Kang W, Zhang P. A comparative study of self-aligned quadruple and sextuple patterning techniques for sub-15nm IC scaling Proceedings of Spie. 8683. DOI: 10.1117/12.2010582  0.457
2012 Chen Y, Kang W, Cheng Q. Intra-cell process variability and compact modeling of LWR effects: from self-aligned multiple patterning to multiple-gate MOSFETs Proceedings of Spie. 8327. DOI: 10.1117/12.916503  0.47
2012 Kang W, Chen Y. Overlay, decomposition and synthesis methodology for hybrid self-aligned triple and negative-tone double patterning Proceedings of Spie. 8327. DOI: 10.1117/12.916495  0.412
2012 Chen Y, Cheng Q, Kang W. Technological Merits, Process Complexity, and Cost Analysis of Self-aligned Multiple Patterning Proceedings of Spie. 8326: 832620. DOI: 10.1117/12.916490  0.443
2012 Chen Y. Maskless EUV lithography: an already difficult technology made even more complicated? Proceedings of Spie. 8323. DOI: 10.1117/12.899967  0.462
2012 Chen Y, Cheng Q, Kang W. Mandrel and spacer engineering based self-aligned triple patterning Proceedings of Spie. 8328. DOI: 10.1117/12.899888  0.469
2012 Chen Y, Cheng Q, Kang W. Analysis of process characteristics of self-aligned multiple patterning Microelectronic Engineering. 98: 184-188. DOI: 10.1016/J.Mee.2012.07.040  0.464
2012 Chen Y. Process optimization and simplification of self-aligned triple patterning Microelectronic Engineering. 98: 590-594. DOI: 10.1016/J.Mee.2012.06.011  0.458
2001 Shroff Y, Chen Y, Oldham W. Fabrication of parallel-plate nanomirror arrays for extreme ultraviolet maskless lithography Journal of Vacuum Science & Technology B. 19: 2412-2415. DOI: 10.1116/1.1417544  0.646
1999 Choksi N, Pickard DS, McCord M, Pease RFW, Shroff Y, Chen Y, Oldham W, Markle D. Maskless extreme ultraviolet lithography Journal of Vacuum Science & Technology B. 17: 3047-3051. DOI: 10.1116/1.590952  0.652
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