Lijun Li, Ph.D. - Publications
Affiliations: | 2006 | University of California, Irvine, Irvine, CA |
Area:
Electronics and Electrical EngineeringYear | Citation | Score | |||
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2011 | Li L, Green MM. Power Optimization of an 11.75-Gb/s Combined Decision Feedback Equalizer and Clock Data Recovery Circuit in 0.18- $\mu\hbox{m}$ CMOS Ieee Transactions On Circuits and Systems. 58: 441-450. DOI: 10.1109/Tcsi.2010.2072190 | 0.408 | |||
2006 | Singh U, Li L, Green MM. A 34 Gb/s distributed 2:1 MUX and CMU using 0.18 μm CMOS Ieee Journal of Solid-State Circuits. 41: 2067-2076. DOI: 10.1109/Jssc.2006.880630 | 0.407 | |||
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