David Pan, Ph.D. - US grants

Proposal ID: 0644316
Title: CAREER: A Synergistic CAD Framework for Nanometer Design and Process
Integration
PI: David Pan
Institution: UT Austin

Abstract:

After four decades of Moore's Law empowered by CMOS scaling, the semiconductor industry is facing unprecedented design and manufacturing challenges. The industry is stuck with the 193nm optical lithography as the dominant integrated circuit manufacturing process, which is likely to remain so for at least another 5 years, for 45nm, 32nm, and even 22nm technology nodes. A prominent feature of the deep sub-wavelength lithography is its proximity, layout-dependent effect. It is estimated that the lithography and design-related yield losses may contribute to 80% or more of the total yield loss in nanometer designs. However, it is not well captured in existing design flows, from modeling to optimization.

This project will develop a synergistic computer aided design (CAD) framework that enables holistic design and process integration. It will resort to the root causes of yield losses by developing a set of design-oriented yet variation-aware manufacturing/yield models, as well as geometrical and electrical characterizations using predictive virtual silicon images. Thus it will help to eliminate significant amount of uncertainties for yield analysis and optimization. Meanwhile, guided by the modeling framework, novel CAD algorithms will be developed at various abstraction levels and architecture explorations will be performed for multi-objective design/manufacturing optimizations. The project will further investigate design and process integration issues for emerging technologies such as nanolithography and hybrid CMOS/post-CMOS processes.

The integrated education component of the project will train a diverse body of students in this highly crosscutting and important area, where the intersection and co-evolution of circuit design, CAD and manufacturing create an excellent opportunity for exposing students to multiple engineering disciplines. Taken together in a holistic manner, this project aims at filling the critical gaps between design/CAD and manufacturing/process to further extend the scaling and economic benefits of the Moore's Law.

Through-Silicon-Via (TSV) provides the possibility of arranging heterogeneous components across multiple dies at a fine level of granularity in 3D ICs. This can result in significant decrease in the overall wire length, delay, power, and form factor. Primarily due to their large size compared with other layout objects, however, TSVs cause significant non-uniform density distribution in various layers. This density issue is expected to cause trouble during chemical mechanical polishing (CMP) and require TSV-aware solutions. In addition, the CTE (coefficient of thermal expansion) mismatch between TSV copper and silicon causes significant thermal mechanical stress to the devices nearby during TSV manufacturing and circuit operation. This in turn affects the timing and power characteristics of the devices. The mechanical reliability of the substrate and devices are also affected by TSVs. However, little is known on what design tool and methodology changes are required to improve the manufacturability of TSV-based 3D ICs. This project would investigate three key DFM/DFR areas specific to 3D IC integration, namely, TSV-induced stress effect and its impact to the overall circuit timing and power, TSV impact to CMP and lithography, and TSV-induced reliability. Successful completion of the project would help us to gain in-depth understanding of manufacturability and reliability issues with 3D ICs and TSV technology and develop effective physical design solutions to overcome these issues. The proposal calls for a very strong collaboration between the researchers from the manufacturability and reliability modeling, simulation, and validation area and the researchers from circuit and physical design area for 3D ICs.

Advancing lithography patterning, which enables feature size scaling, has been a holy grail for the semiconductor industry. There are several leading nanolithography technologies for 14nm, 11nm, 7nm and 1x nm for extreme scaling, including multiple patterning lithography (MPL), extreme ultraviolet lithography (EUVL) and e-beam lithography (EBL). This project aims at developing novel design for manufacturability algorithms, tools, and methodologies for nanometer integrated circuits (IC) manufactured through these emerging nanolithography technologies. The proposed research will synergistically link nanolithography process modeling/abstraction with multi-scale layout optimization. For MPL, robust and scalable multi-objective layout decomposition algorithms and MPL-aware physical design tools will be developed. For next-generation nanolithography such as EUVL and EBL, new design and process integration issues will be studied. Hybrid nanolithography (e.g., combining MPL with EBL) will also be explored to shed light on ultimate nano-patterning for future IC layout design. The proposed solutions will span multiple technology layers and bring together experts from both academia and industry.

This proposed project addresses fundamental challenges to bridge the gap between IC design and manufacturing in extreme scaling. Thus its potential impacts to the semiconductor industry and associated information and high-tech industries cannot be overstated. The academia-industry collaboration between University of Texas and IBM promises innovative and high-risk academia research coupled with realistic industry data/benchmarks and timely technology transfer through IBM and its global partners to benefit the overall industry. The highly interdisciplinary nature of this research will be tightly integrated into a variety of curriculum development and diverse student mentoring programs.

Designing robust and energy-efficient large-scale systems-on-chips (SOCs) with high design productivity is a challenge of great interest. However, lack of coordination among different design layers has caused designers to make worst-case assumptions at individual design layers, leading to substantially suboptimal designs with poor reliability/energy/performance co-optimization or tradeoffs. This project is the first major effort dedicated toward a unified failure-resistant system from high-level synthesis to physical design with tight integration. It will build reliability-centric physical-aware high-level synthesis and high-level-guided physical design to bridge the gap between these two distant layers. A novel cross-layer engineering change order (ECO) framework will also be developed to couple high-level ECO with stable physical-level ECO. New tools and methodologies will be studied and provided to the system and physical design community targeting reliability while increasing overall design productivity and quality.

Electronics have permeated modern society, which increasingly depends on reliable operations of these electronic systems. However, device-level scaling is heading in the opposite direction from system reliability. This project will transform existing SOC design methodologies through cross-layer integration. Research from this effort will be broadly disseminated through publications and presentations, active interaction with industrial collaborators, as well as infusion of new course material into classrooms and instructional laboratories. The principal investigators will continue their efforts in recruiting women and other underrepresented minorities into their research programs. They have previously reached out to K-12 students and will continue to do so in order to attract the best of them into the engineering profession.

The goal of the proposed research is to tackle two critical challenges for conventional analog and mixed-signal circuits to address scaling incompatibility and low design productivity. The proposed time-domain analog mixed signal circuits are scaling compatible, and can achieve higher performance with substantially reduced chip area, power, and cost. They address the critical real-world challenge of cost effectively integrating analog-mixed-signal circuits with digital functions. They can enable emerging applications that demand ultra-low-power and ultra-low voltage solutions. The proposed research design for synthesizability and new synthesis tools also has significant impacts on enhancing design productivity, leading to reduced cost, enhanced capability, shortened time-to-market, and improved reliability.

The proposed novel time domain analog-mixed-signal circuits process analog information in the time or phase domain. Thus, they naturally benefit from CMOS scaling with increased transistor speed and reduced delay. Moreover, this proposal opens up a new research direction of analog-mixed-signal design for synthesizability, the objective of which is to alleviate the difficulty in analog synthesis by intentionally creating new topologies that are synthesis friendly. New analog synthesis tools will be developed, with focus on developing compact and high-fidelity models to reduce runtime and tackle process variation. Several previously untouched issues will be addressed, such as sensitive node protection, current flow constraints, and substrate noise coupling. A new machine-learning based framework will also be developed to further increase automation level.

At present, almost all analog integrated circuits (ICs) are designed manually, leading to low productivity and low performance. The goal of this research project is to change the way analog circuits are designed by significantly increasing design automation. If successful, it will greatly shorten the time-to-market, increase the system capability, reduce the design cost, and lower the chip failure rate. The proposed research topic bridges the circuit design community with the electronic design automation (EDA) community, initiating collaboration and co-development. On the application side, the proposed novel analog circuit design methodology will serve as the catalyst for emerging applications, such as IoT, 5G cellular communication, wearable electronics, and self-driving vehicles. On the educational side, a new and dedicated course will be developed to facilitate designers to adopt the proposed novel analog IC design methodology. The PIs will also continue their active roles in graduate student mentoring, minority outreach, local community service, and settling up close ties between UT Austin and local industry.


There are two existing analog design flows in existence today. One is the classic manual design methodology. Despite wide acceptance, it has low productivity and low accuracy, which results from the hard fact that human beings are inefficient at complicated numerical computation and multi-dimensional optimization. The other is analog IC design automation (ADA), which treats circuit design as a black-box optimization problem and solves it by powerful optimization algorithms. Despite its high efficiency, ADA has received limited acceptance due to unreliability. The algorithms do not understand circuits, leading to unpractical synthesis results that only make numerical sense. Analog IC design is complex both in high-level reasoning and low-level computation, thus, neither human nor algorithm alone is adequate. To address this dilemma, a new analog IC design methodology that integrates both human and machine intelligence (HMI) is proposed. Its goal is to place the designers at the center and empower them with novel interactive tools. The specific research thrusts of this project include: 1) HMI guided interactive schematic design tools; 2) HMI guided interactive layout design tools; 3) HMI guided interactive analog design methodology and silicon validation; 4) HMI guided interactive circuit architecture selection and creation; 5) overall framework and toolkit.

As the semiconductor industry reaches 10nm/7nm technology nodes and beyond, more innovations will be realized through alternative or emerging scaling such as novel process/material and device engineering to seek equivalent scaling effects. Such scaling demands closer design and technology co-optimization and explorations. This project will seek to develop novel CAD algorithms, tools, and methodologies to bridge the future IC design and technology gaps in the new era of emerging scaling. The proposed research, if successful, will have tremendous impacts on the $350 billion semiconductor industry which is at a critical point, transitioning from conventional scaling to emerging scaling. The PI will work with industry collaborators for technology transfer to benefit the overall industry and society. The highly interdisciplinary nature of this research will be tightly integrated into curriculum development and student training/outreach activities.

The technical problems to be addressed include: (1) new sub-resolution directed-self-assembly (DSA) patterning and layout co-optimizations; (2) new mask and layout optimizations for future hybrid lithography technologies considering emerging processes/materials and design requirements; (3) future standard cell and routing architecture exploration; (4) physical design for next-generation nano-devices.

ABSTRACT A recent U.S. survey indicated that 40% of US adults are obese, and a worldwide survey of 195 countries showed that 2.2 billion people globally are obese or overweight. It would be vital to understand the genetic mechanisms and gene-environment interactions that underlie obesity-related phenotypes to improve treatment options and drug development to combat this global obesity epidemic. This emphasizes the need to discover additional DNA variants contributing to obesity. The goal of this project is to improve the understanding of genetic regulatory mechanisms of gene expression in obesity-related pathways in human adipocytes and adipose tissue. In Aim 1, we will integrate promoter Capture Hi-C (pCHi-C) data produced in primary Human White Adipocytes (HWAs), which elucidates the physical interaction between enhancers and promoters, with genotype, obesogenic phenotypes, and adipose tissue transcriptomic data from the Finnish METabolic Syndrome in Men (METSIM) cohort to directly follow up the looping cis expression quantitative trait loci (eQTLs) and BMI-correlated genes identified in my first paper (Pan et al. Nature Communications, 2018 in press). Our preliminary data show that looping cis-eQTLs in DNAse I Hypersensitivity sites (DHSs) significantly contribute to the variation in local gene expression. In Aim 1, we will refine this analysis of cis-eQTLs in DHSs using Assay for Transposase-Accessible Chromatin using sequencing (ATAC-seq) in primary HWAs to identify the open chromatin regions in HWAs, a currently publically unavailable dataset. We will incorporate ATAC-seq data to identify the variants in regions of open chromatin within the chromosomal interactions where proteins, such as transcription factors (TFs), may bind. We will also use our previously identified list of 38 non-GWAS BMI-correlated genes as our obesity candidates, potentially reacting to obesogenic cellular environment via differential TF binding. Using Systematic high-resolution activation and repression profiling with the reporter- tiling Massively Parallel Reporter Assay (SHARPR-MPRA), we will confirm the enhancer potential of the looping cis-eQTL for the 38 BMI-correlated genes and search for their networks related to obesogenic phenotypes in METSIM using Weighted Gene Coexpression Network Analysis (WGCNA). In Aim 2, we propose to identify longer range trans-eQTLs mediated by looping cis-eQTLs and cis-genes. Using the TFs identified in obesogenic networks from WGCNA as potential cis-genes, we aim to discover their cis-eQTLs and then examine if those cis-eQTLs are also trans-eQTLs, confirming thus the direction of effect in a mediation analysis. The gene regulatory architecture that we identify and their obesogenic networks should help further the understanding of the genetic mechanisms that underlie adipose and adipocyte biology and provide potential clinically actionable targets for obesity. Aims 1 and 2 align with the mission of the National Institute of Diabetes and Digestive and Kidney Diseases (NIDDK) to decrease the prevalence of obesity and cardiometabolic disorders through the understanding of the underlying molecular mechanisms.