Amir Amirkhany, Ph.D.
Affiliations: | 2008 | Stanford University, Palo Alto, CA |
Area:
Electrical Engineering, Computer scienceGoogle:
"Amir Amirkhany"Mean distance: 7046.11
Parents
Sign in to add mentorMark Horowitz | grad student | 2008 | Stanford | |
(Multi-carrier signaling for high-speed electrical links.) |
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Publications
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Kaviani K, Amirkhany A, Huang C, et al. (2013) A 0.4-mW/Gb/s near-ground receiver front-end with replica transconductance termination calibration for a 16-Gb/s source-series terminated transceiver Ieee Journal of Solid-State Circuits. 48: 636-648 |
Kaviani K, Wu T, Wei J, et al. (2012) A Tri-modal 20-Gbps/link differential/DDR3/GDDR5 memory interface Ieee Journal of Solid-State Circuits. 47: 926-937 |
Amirkhany A, Wei J, Mishra N, et al. (2011) A 12.8-Gb/s/link tri-modal single-ended memory interface for graphics applications Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 232-233 |
Aryanfar F, Amirkhany A. (2010) A low-cost resonance mitigation technique for multidrop memory interfaces Ieee Transactions On Circuits and Systems Ii: Express Briefs. 57: 339-342 |
Ahmadi MR, Amirkhany A, Harjani R. (2010) A 5 Gbps 0.13 μm CMOS pilot-based clock and data recovery scheme for high-speed links Ieee Journal of Solid-State Circuits. 45: 1533-1541 |
Savoj J, Abbasfar A, Amirkhany A, et al. (2008) A 12-GS/s phase-calibrated CMOS digital-to-analog converter for backplane communications Ieee Journal of Solid-State Circuits. 43: 1207-1215 |
Amirkhany A, Abbasfar A, Savoj J, et al. (2008) A 24 Gb/s software programmable analog multi-tone transmitter Ieee Journal of Solid-State Circuits. 43: 999-1008 |