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Tetsuya Asai

Affiliations: 
Hokkaido University, Sapporo-shi, Hokkaidō, Japan 
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"Tetsuya Asai"
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Parents

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Tomoki Fukai grad student 1994-1996

Children

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Kazuki Nakada grad student 2002-2005 Hokkaido University

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Publications

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Momose H, Kaneko T, Asai T. (2020) Systems and circuits for AI chips and their trends Japanese Journal of Applied Physics. 59: 050502
Hirayama Y, Asai T, Motomura M, et al. (2020) A Hardware-efficient Weight Sampling Circuit for Bayesian Neural Networks International Journal of Networking and Computing. 10: 84-93
Ando K, Ueyoshi K, Oba Y, et al. (2019) Dither NN: Hardware/Algorithm Co-Design for Accurate Quantized Neural Networks Ieice Transactions On Information and Systems. 102: 2341-2353
Tanaka H, Akai-Kasaya M, TermehYousefi A, et al. (2018) A molecular neuromorphic network device consisting of single-walled carbon nanotubes complexed with polyoxometalate. Nature Communications. 9: 2693
Tanibata A, Schmid A, Takamaeda-Yamazaki S, et al. (2018) Protocomputing Architecture over a Digital Medium Aiming at Real-Time Video Processing Complexity. 2018: 1-11
Ando K, Ueyoshi K, Orimo K, et al. (2018) BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W Ieee Journal of Solid-State Circuits. 53: 983-994
Ando K, Takamaeda-Yamazaki S, Ikebe M, et al. (2017) A Multithreaded CGRA for Convolutional Neural Network Processing Circuits and Systems. 8: 149-170
Hida I, Takamaeda-Yamazaki S, Ikebe M, et al. (2017) A High Performance and Energy Efficient Microprocessor with a Novel Restricted Dynamically Reconfigurable Accelerator Circuits and Systems. 8: 134-147
Ueyoshi K, Marukame T, Asai T, et al. (2016) FPGA Implementation of a Scalable and Highly Parallel Architecture for Restricted Boltzmann Machines Circuits and Systems. 7: 2132-2141
Nakada K, Miura K, Asai T. (2016) Dynamical systems design of silicon neurons using phase reduction method Nonlinear Theory and Its Applications, Ieice. 7: 95-109
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