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Rohit S. Shenoy, Ph.D. - Publications

Affiliations: 
2005 Stanford University, Palo Alto, CA 
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17 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2015 Padilla A, Burr GW, Shenoy RS, Raman KV, Bethune DS, Shelby RM, Rettner CT, Mohammad J, Virwani K, Narayanan P, Deb AK, Pandey RK, Bajaj M, Murali KVRM, Kurdi BN, et al. On the origin of steep i - V nonlinearity in mixed-ionic-electronic-conduction-based access devices Ieee Transactions On Electron Devices. 62: 963-971. DOI: 10.1109/Ted.2015.2389832  0.335
2015 Narayanan P, Burr GW, Shenoy RS, Stephens S, Virwani K, Padilla A, Kurdi BN, Gopalakrishnan K. Exploring the design space for crossbar arrays built with mixed-ionic-electronic-conduction (MIEC) access devices Ieee Journal of the Electron Devices Society. 3: 423-434. DOI: 10.1109/Jeds.2015.2442242  0.331
2015 Narayanan P, Burr GW, Shenoy RS, Virwani K, Kurdi B. Circuit-level benchmarking of access devices for resistive nonvolatile memory arrays Technical Digest - International Electron Devices Meeting, Iedm. 2015: 29.7.1-29.7.4. DOI: 10.1109/IEDM.2014.7047137  0.328
2014 Burr GW, Shenoy RS, Virwani K, Narayanan P, Padilla A, Kurdi B, Hwang H. Access devices for 3D crosspoint memory Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures. 32. DOI: 10.1116/1.4889999  0.34
2014 Shenoy RS, Burr GW, Virwani K, Jackson B, Padilla A, Narayanan P, Rettner CT, Shelby RM, Bethune DS, Raman KV, Brightsky M, Joseph E, Rice PM, Topuria T, Kellock AJ, et al. MIEC (mixed-ionic-electronic-conduction)-based access devices for non-volatile crossbar memory arrays Semiconductor Science and Technology. 29. DOI: 10.1088/0268-1242/29/10/104005  0.451
2012 Burr GW, Virwani K, Shenoy RS, Padilla A, BrightSky M, Joseph EA, Lofaro M, Kellock AJ, King RS, Nguyen K, Bowers AN, Jurich M, Rettner CT, Jackson B, Bethune DS, et al. Large-scale (512kbit) integration of multilayer-ready access-devices based on Mixed-Ionic-Electronic-Conduction (MIEC) at 100% yield Digest of Technical Papers - Symposium On Vlsi Technology. 41-42. DOI: 10.1109/VLSIT.2012.6242451  0.342
2012 Virwani K, Burr GW, Shenoy RS, Rettner CT, Padilla A, Topuria T, Rice PM, Ho G, King RS, Nguyen K, Bowers AN, Jurich M, Brightsky M, Joseph EA, Kellock AJ, et al. Sub-30nm scaling and high-speed operation of fully-confined Access-Devices for 3D crosspoint memory based on mixed-ionic-electronic-conduction (MIEC) materials Technical Digest - International Electron Devices Meeting, Iedm. 2.7.1-2.7.4. DOI: 10.1109/IEDM.2012.6478967  0.389
2011 Shenoy RS, Gopalakrishnan K, Jackson B, Virwani K, Burr GW, Rettner CT, Padilla A, Bethune DS, Shelby RM, Kellock AJ, Breitwisch M, Joseph EA, Dasaka R, King RS, Nguyen K, et al. Endurance and scaling trends of novel access-devices for multi-layer crosspoint-memory based on mixed-ionic-electronic-conduction (MIEC) materials Digest of Technical Papers - Symposium On Vlsi Technology. 94-95.  0.342
2010 Burr GW, Breitwisch MJ, Franceschini M, Garetto D, Gopalakrishnan K, Jackson B, Kurdi B, Lam C, Lastras LA, Padilla A, Rajendran B, Raoux S, Shenoy RS. Phase change memory technology Journal of Vacuum Science and Technology B:Nanotechnology and Microelectronics. 28: 223-262. DOI: 10.1116/1.3301579  0.322
2008 Schmid GM, Khusnatdinov N, Brooks CB, LaBrake D, Thompson E, Resnick DJ, Owens J, Ford A, Sasaki S, Toyama N, Kurihara M, Hayashi N, Kobayashi H, Sato T, Nagarekawa O, ... ... Shenoy R, et al. Controlling linewidth roughness in step and flash imprint lithography Proceedings of Spie - the International Society For Optical Engineering. 6792. DOI: 10.1117/12.798936  0.386
2007 Rajendran B, Shenoy RS, Witte DJ, Chokshi NS, DeLeon RL, Tompa GS, Pease RFW. Low thermal budget processing for sequential 3-D IC fabrication Ieee Transactions On Electron Devices. 54: 707-714. DOI: 10.1109/Ted.2007.891300  0.4
2007 Kapur P, Shenoy RS, Saraswat KC. Power/performance based scalability comparisons between conventional and novel transistors down to 32nm technology node International Conference On Simulation of Semiconductor Processes and Devices, Sispad. 290-293. DOI: 10.1109/SISPAD.2006.282893  0.463
2005 Gopalakrishnan K, Woo R, Shenoy R, Jono Y, Griffin PB, Plummer JD. Novel very high IE structures based on the directed BBHE mechanism for ultralow-power flash memories Ieee Electron Device Letters. 26: 212-215. DOI: 10.1109/Led.2005.843784  0.379
2005 Rajendran B, Shenoy RS, Witte DJ, Chokshi NS, DeLeon RL, Tompa GS, Pease RFW. CMOS transistor processing compatible with monolithic 3-D integration 2005 Proceedings - 22nd International Vlsi Multilevel Interconnection Conference, Vmic 2005. 76-82.  0.412
2004 Shenoy RS, Saraswat KC. Novel process for fully self-aligned planar ultrathin body double gate FET Proceedings - Ieee International Soi Conference. 190-191.  0.368
2004 Kapur P, Shenoy RS, Chao AK, Nishi Y, Saraswat KC. Power optimization of future transistors and a resulting global comparison standard Technical Digest - International Electron Devices Meeting, Iedm. 415-418.  0.422
2003 Shenoy RS, Saraswat KC. Optimization of extrinsic source/drain resistance in ultrathin body double-gate FETs Ieee Transactions On Nanotechnology. 2: 265-270. DOI: 10.1109/TNANO.2003.820780  0.568
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