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Payman Zarkesh-Ha, Ph.D. - Publications

Affiliations: 
2001 Georgia Institute of Technology, Atlanta, GA 
Area:
Microelectronics/Microsystems
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32 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Nezhadbadeh S, Neumann A, Zarkesh-Ha P, Brueck SRJ. Chirped-grating spectrometer-on-a-chip. Optics Express. 28: 24501-24510. PMID 32906990 DOI: 10.1364/Oe.398072  0.386
2017 Fahs B, Chowdhury AJ, Zhang Y, Ghasemi J, Hitchcock C, Zarkesh-Ha P, Hella MM. Design and Modeling of Blue-Enhanced and Bandwidth-Extended PN Photodiode in Standard CMOS Technology Ieee Transactions On Electron Devices. 64: 2859-2866. DOI: 10.1109/Ted.2017.2700389  0.312
2016 Fiorante GRC, Ghasemi J, Zarkesh-Ha P, Krishna S. Spatio-Temporal Bias-Tunable Readout Circuit for On-Chip Intelligent Image Processing Ieee Transactions On Circuits and Systems I: Regular Papers. 63: 1825-1832. DOI: 10.1109/Tcsi.2016.2593991  0.37
2016 Fahs B, Chellis J, Senneca MJ, Chowdhury A, Ray S, Mirvakili A, Mazzara B, Zhang Y, Ghasemi J, Miao Y, Zarkesh-Ha P, Koomson VJ, Hella MM. A 6-m OOK VLC Link Using CMOS-Compatible p-n Photodiode and Red LED Ieee Photonics Technology Letters. 28: 2846-2849. DOI: 10.1109/Lpt.2016.2623558  0.33
2015 Neumann A, Ghasemi J, Nezhadbadeh S, Nie X, Zarkesh-Ha P, Brueck SR. CMOS-compatible plenoptic detector for LED lighting applications. Optics Express. 23: 23208-16. PMID 26368423 DOI: 10.1364/Oe.23.023208  0.301
2014 Atghiaee A, Masoumi N, Zarkesh-Ha P, Mehri M. Predictive application of PIDF and PPC for interconnects' crosstalk, TSV, and LER issues in UDSM ICs and nano-systems Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 22: 438-443. DOI: 10.1109/Tvlsi.2013.2243849  0.334
2012 Jang WY, Hayat MM, Zarkesh-Ha P, Krishna S. Continuous time-varying biasing approach for spectrally tunable infrared detectors. Optics Express. 20: 29823-37. PMID 23388809 DOI: 10.1364/Oe.20.029823  0.314
2011 Zarkesh-Ha P, Shahi AAM. Stochastic analysis and design guidelines for CNFETs in gigascale integrated systems Ieee Transactions On Electron Devices. 58: 530-539. DOI: 10.1109/Ted.2010.2092780  0.367
2011 Xu JF, Fiorante GRC, Zarkesh-Ha P, Krishna S. A Readout Integrated Circuit (ROIC) with hybrid source/sensor array Ieee Photonic Society 24th Annual Meeting, Pho 2011. 97-98. DOI: 10.1109/Pho.2011.6110443  0.373
2010 Zarkesh-Ha P, Jang W, Nguyen P, Khoshakhlagh A, Xu J. A reconfigurable ROIC for integrated infrared spectral sensing 2010 23rd Annual Meeting of the Ieee Photonics Society, Photinics 2010. 714-715. DOI: 10.1109/Photonics.2010.5699088  0.353
2009 Ghaida RS, Doniger K, Zarkesh-Ha P. Random yield prediction based on a stochastic layout sensitivity model Ieee Transactions On Semiconductor Manufacturing. 22: 329-337. DOI: 10.1109/Tsm.2009.2024821  0.344
2009 Ghaida RS, Zarkesh-Ha P. A layout sensitivity model for eestimating electromigration-vulnerable narrow interconnects Journal of Electronic Testing: Theory and Applications (Jetta). 25: 67-77. DOI: 10.1007/S10836-008-5079-X  0.352
2008 Mallajosyula A, Zarkesh-Ha P. A robust single event upset hardened clock distribution network Ieee International Integrated Reliability Workshop Final Report. 121-124. DOI: 10.1109/IRWS.2008.4796101  0.306
2007 Sarvari R, Naeemi A, Zarkesh-Ha P, Meindl JD. Design and optimization for nanoscale power distribution networks in gigascale systems Proceedings of the Ieee 2007 International Interconnect Technology Conference - Digest of Technical Papers. 190-192.  0.711
2004 Joyner JW, Zarkesh-Ha P, Meindl JD. Global interconnect design in a three-dimensional system-on-a-chip Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 12: 367-372. DOI: 10.1109/Tvlsi.2004.825835  0.751
2004 Zarkesh-Ha P, Doniger K, Loh W, Bendix P. Prediction of interconnect adjacency distribution: Derivation, validation, and applications International Workshop On System Level Interconnect Prediction, Slip. 99-106.  0.347
2003 Zarkesh-Ha P, Doniger K, Loh W, Sun D, Stephani R, Priebe G. A compact model for analysis and design of on-chip power network with decoupling capacitors Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 84-89.  0.317
2002 Meindl JD, Davis JA, Zarkesh-Ha P, Patel CS, Martin KP, Kohl PA. Interconnect opportunities for gigascale integration Ibm Journal of Research and Development. 46: 245-263. DOI: 10.1147/Rd.462.0245  0.735
2001 Joyner JW, Venkatesan R, Zarkesh-Ha P, Davis JA, Meindl JD. Impact of three-dimensional architectures on interconnects in gigascale integration Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 9: 922-928. DOI: 10.1109/92.974905  0.745
2001 Meindl JD, Venkatesan R, Davis JA, Joyner J, Naeemi A, Zarkesh-Ha P, Bakir M, Mulé T, Kohl PA, Martin KP. Interconnecting device opportunities for gigascale integration (GSI) Technical Digest - International Electron Devices Meeting. 525-528.  0.734
2001 Joyner JW, Zarkesh-Ha P, Meindl JD. A stochastic global net-length distribution for a three-dimensional system-on-a-chip (3D-SoC) Proceedings of the Annual Ieee International Asic Conference and Exhibit. 147-151.  0.757
2001 Naeemi A, Patel CS, Bakir MS, Zarkesh-Ha P, Martin KP, Meindl JD. Sea of leads: A disruptive paradigm for a system-on-a-chip (SoC) Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 280-281.  0.723
2001 Saint-Laurent M, Zarkesh-Ha P, Swaminathan M, Meindl JD. Optimal clock distribution with an array of phase-locked loops for multiprocessor chips Midwest Symposium On Circuits and Systems. 1: 454-457.  0.334
2000 Joyner JW, Zarkesh-Ha P, Davis JA, Meindl JD. A three-dimensional stochastic wire-length distribution for variable separation of strata Proceedings of the Ieee 2000 International Interconnect Technology Conference, Iitc 2000. 126-128. DOI: 10.1109/IITC.2000.854301  0.755
2000 Chen Q, Davis JA, Zarkesh-Ha P, Meindl JD. A novel via blockage model and its implications Proceedings of the Ieee 2000 International Interconnect Technology Conference, Iitc 2000. 15-17. DOI: 10.1109/IITC.2000.854267  0.368
2000 Chen Q, Davis JA, Zarkesh-Ha P, Meindl JD. A compact physical via blockage model Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 8: 689-692. DOI: 10.1109/92.902263  0.571
2000 Zarkesh-Ha P, Davis JA, Meindl JD. Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 8: 649-659. DOI: 10.1109/92.902259  0.571
2000 Joyner JW, Zarkesh-Ha P, Davis JA, Meindl JD. Vertical pitch limitations on performance enhancement in bonded three-dimensional interconnect architectures International Workshop On System-Level Interconnect Prediction (Slip 2000). 123-127.  0.764
2000 Naeemi A, Zarkesh-Ha P, Patel CS, Meindl JD. Performance improvement using on-board wires for on-chip interconnects Ieee Topical Meeting On Electrical Performance of Electronic Packaging. 325-328.  0.572
2000 Zarkesh-Ha P, Meindl JD. Integrated architecture for global interconnects in a gigascale system-on-a-chip (GSoC) Digest of Technical Papers - Symposium On Vlsi Technology. 194-195.  0.425
2000 Zarkesh-Ha P, Davis JA, Loh W, Meindl JD. Prediction of interconnect fan-out distribution using Rent's rule International Workshop On System-Level Interconnect Prediction (Slip 2000). 107-112.  0.523
1999 Zarkesh-Ha P, Meindl JD. Asymptotically zero power dissipation gigahertz clock distribution networks Ieee Topical Meeting On Electrical Performance of Electronic Packaging. 57-60.  0.305
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