| Year |
Citation |
Score |
| 2020 |
Liao Y, Pan C, Naeemi A. Benchmarking and Optimization of Spintronic Memory Arrays Ieee Journal On Exploratory Solid-State Computational Devices and Circuits. 6: 9-17. DOI: 10.1109/Jxcdc.2020.2999270 |
0.327 |
|
| 2020 |
Noor SL, Dens K, Reynaert P, Catthoor F, Lin D, Dorpe PV, Naeemi A. Modeling and Optimization of Plasmonic Detectors for Beyond-CMOS Plasmonic Majority Logic Gates Journal of Lightwave Technology. 38: 5092-5099. DOI: 10.1109/Jlt.2020.2998014 |
0.31 |
|
| 2020 |
Li X, Lin S, Dc M, Liao Y, Yao C, Naeemi A, Tsai W, Wang SX. Materials Requirements of High-Speed and Low-Power Spin-Orbit-Torque Magnetic Random-Access Memory Ieee Journal of the Electron Devices Society. 8: 674-680. DOI: 10.1109/Jeds.2020.2984610 |
0.301 |
|
| 2019 |
Lou Q, Pan C, McGuinness J, Horvath A, Naeemi A, Niemier M, Hu XS. A Mixed Signal Architecture for Convolutional Neural Networks Acm Journal On Emerging Technologies in Computing Systems. 15: 1-26. DOI: 10.1145/3304110 |
0.306 |
|
| 2019 |
Naeemi A. Special Topic on Ferroelectric Transistors for Advanced Logic, Analog, and Memory Applications Ieee Journal On Exploratory Solid-State Computational Devices and Circuits. 5: ii-iii. DOI: 10.1109/Jxcdc.2019.2960623 |
0.337 |
|
| 2019 |
Pan C, Lou Q, Niemier M, Hu S, Naeemi A. Energy-Efficient Convolutional Neural Network Based on Cellular Neural Network Using Beyond-CMOS Technologies Ieee Journal On Exploratory Solid-State Computational Devices and Circuits. 5: 85-93. DOI: 10.1109/Jxcdc.2019.2960307 |
0.344 |
|
| 2018 |
Pan C, Naeemi A. Transient Performance Analysis and Optimization of Crossbar Memory Arrays Using NbO2-Based Threshold Switching Selectors Ieee Transactions On Electron Devices. 65: 3214-3220. DOI: 10.1109/Ted.2018.2848844 |
0.312 |
|
| 2018 |
Hsu C, Pan C, Naeemi A. Performance Analysis and Enhancement of Negative Capacitance Logic Devices Based on Internally Resistive Ferroelectrics Ieee Electron Device Letters. 39: 765-768. DOI: 10.1109/Led.2018.2820118 |
0.332 |
|
| 2018 |
Pan C, Naeemi A. Complementary Logic Implementation for Antiferromagnet Field-Effect Transistors Ieee Journal On Exploratory Solid-State Computational Devices and Circuits. 4: 69-75. DOI: 10.1109/Jxcdc.2018.2878635 |
0.331 |
|
| 2017 |
Dutta S, Zografos O, Gurunarayanan S, Radu I, Soree B, Catthoor F, Naeemi A. Proposal for nanoscale cascaded plasmonic majority gates for non-Boolean computation. Scientific Reports. 7: 17866. PMID 29259222 DOI: 10.1038/S41598-017-17954-2 |
0.308 |
|
| 2017 |
Prasad D, Pan C, Naeemi A. Modeling Interconnect Variability at Advanced Technology Nodes and Potential Solutions Ieee Transactions On Electron Devices. 64: 1246-1253. DOI: 10.1109/Ted.2016.2645448 |
0.303 |
|
| 2017 |
Pan C, Naeemi A. An Expanded Benchmarking of Beyond-CMOS Devices Based on Boolean and Neuromorphic Representative Circuits Ieee Journal On Exploratory Solid-State Computational Devices and Circuits. 3: 101-110. DOI: 10.1109/Jxcdc.2018.2793536 |
0.322 |
|
| 2017 |
Mousavi Iraei R, Manipatruni S, Nikonov DE, Young IA, Naeemi A. Electrical-Spin Transduction for CMOS-Spintronic Interface and Long-Range Interconnects Ieee Journal On Exploratory Solid-State Computational Devices and Circuits. 3: 47-55. DOI: 10.1109/Jxcdc.2017.2706671 |
0.327 |
|
| 2016 |
Pan C, Naeemi A. A proposal for energy-efficient cellular neural network based on spintronic devices Ieee Transactions On Nanotechnology. 15: 820-827. DOI: 10.1109/Tnano.2016.2598147 |
0.355 |
|
| 2016 |
Aghasi H, Iraei RM, Naeemi A, Afshari E. Smart detector cell: A scalable all-spin circuit for low power non-boolean pattern recognition Ieee Transactions On Nanotechnology. 15: 356-366. DOI: 10.1109/Tnano.2016.2530779 |
0.315 |
|
| 2016 |
Kani N, Rakheja S, Naeemi A. A Probability-Density Function Approach to Capture the Stochastic Dynamics of the Nanomagnet and Impact on Circuit Performance Ieee Transactions On Electron Devices. 63: 4119-4126. DOI: 10.1109/Ted.2016.2594170 |
0.332 |
|
| 2016 |
Zhang X, Kumar V, Oh H, Zheng L, May GS, Naeemi A, Bakir MS. Impact of On-Chip Interconnect on the Performance of 3-D Integrated Circuits with Through-Silicon Vias: Part II Ieee Transactions On Electron Devices. 63: 2510-2516. DOI: 10.1109/TED.2016.2556693 |
0.549 |
|
| 2016 |
Kumar V, Oh H, Zhang X, Zheng L, Bakir MS, Naeemi A. Impact of On-Chip Interconnect on the Performance of 3-D Integrated Circuits With Through Silicon Vias: Part I Ieee Transactions On Electron Devices. DOI: 10.1109/Ted.2016.2556693 |
0.594 |
|
| 2016 |
Pan C, Naeemi A. Interconnect design and benchmarking for charge-based beyond-CMOS device proposals Ieee Electron Device Letters. 37: 508-511. DOI: 10.1109/Led.2016.2532350 |
0.337 |
|
| 2016 |
Pan C, Naeemi A. Non-Boolean Computing Benchmarking for Beyond-CMOS Devices Based on Cellular Neural Network Ieee Journal On Exploratory Solid-State Computational Devices and Circuits. 2: 36-43. DOI: 10.1109/Jxcdc.2016.2633251 |
0.332 |
|
| 2015 |
Prasad D, Ceyhan A, Pan C, Naeemi A. Adapting Interconnect Technology to Multigate Transistors for Optimum Performance Ieee Transactions On Electron Devices. 62: 3938-3944. DOI: 10.1109/Ted.2015.2487888 |
0.374 |
|
| 2015 |
Dutta S, Nikonov DE, Manipatruni S, Young IA, Naeemi A. Compact Physical Model for Crosstalk in Spin-Wave Interconnects Ieee Transactions On Electron Devices. 62: 3863-3869. DOI: 10.1109/Ted.2015.2478842 |
0.305 |
|
| 2015 |
Pan C, Raghavan P, Yakimets D, Debacker P, Catthoor F, Collaert N, Tokei Z, Verkest D, Thean AVY, Naeemi A. Technology/System Codesign and Benchmarking for Lateral and Vertical GAA Nanowire FETs at 5-nm Technology Node Ieee Transactions On Electron Devices. DOI: 10.1109/Ted.2015.2461457 |
0.327 |
|
| 2015 |
Pan C, Raghavan P, Ceyhan A, Catthoor F, Tokei Z, Naeemi A. Technology/circuit/system co-optimization and benchmarking for multilayer graphene interconnects at sub-10-nm technology node Ieee Transactions On Electron Devices. 62: 1530-1536. DOI: 10.1109/Ted.2015.2409875 |
0.329 |
|
| 2015 |
Ceyhan A, Jung M, Panth S, Lim SK, Naeemi A. Evaluating Chip-Level Impact of Cu/Low-κ Performance Degradation on Circuit Performance at Future Technology Nodes Ieee Transactions On Electron Devices. DOI: 10.1109/Ted.2015.2394407 |
0.38 |
|
| 2015 |
Pan C, Naeemi A. A paradigm shift in local interconnect technology design in the era of nanoscale multigate and gate-all-around devices Ieee Electron Device Letters. 36: 274-276. DOI: 10.1109/Led.2015.2394366 |
0.367 |
|
| 2015 |
Chang SC, Dutta S, Manipatruni S, Nikonov DE, Young IA, Naeemi A. Interconnects for All-Spin Logic Using Automotion of Domain Walls Ieee Journal On Exploratory Solid-State Computational Devices and Circuits. 1: 49-57. DOI: 10.1109/Jxcdc.2015.2448415 |
0.331 |
|
| 2015 |
Pan C, Naeemi A. A fast system-level design methodology for heterogeneous multi-core processors using emerging technologies Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 5: 75-87. DOI: 10.1109/Jetcas.2015.2398218 |
0.406 |
|
| 2014 |
Kumar V, Sharma R, Uzunlar E, Zheng L, Bashirullah R, Kohl P, Bakir MS, Naeemi A. Airgap interconnects: Modeling, optimization, and benchmarking for backplane, PCB, and interposer applications Ieee Transactions On Components, Packaging and Manufacturing Technology. 4: 1335-1346. DOI: 10.1109/Tcpmt.2014.2326798 |
0.563 |
|
| 2014 |
Pan C, Naeemi A. A proposal for a novel hybrid interconnect technology for the end of roadmap Ieee Electron Device Letters. 35: 250-252. DOI: 10.1109/Led.2013.2291783 |
0.319 |
|
| 2013 |
Ceyhan A, Naeemi A. Cu/Low-k interconnect technology design and benchmarking for future technology nodes Ieee Transactions On Electron Devices. 60: 4041-4047. DOI: 10.1109/Ted.2013.2286176 |
0.348 |
|
| 2013 |
Ceyhan A, Naeemi A. Cu interconnect limitations and opportunities for SWNT interconnects at the end of the roadmap Ieee Transactions On Electron Devices. 60: 374-382. DOI: 10.1109/Ted.2012.2224663 |
0.377 |
|
| 2013 |
Rakheja S, Naeemi A. Communicating novel computational state variables: Post-CMOS logic Ieee Nanotechnology Magazine. 7: 15-23. DOI: 10.1109/Mnano.2012.2237314 |
0.311 |
|
| 2013 |
Zheng P, Bryan SE, Yang Y, Murali R, Naeemi A, Meindl JD. Hydrogenation of graphene nanoribbon edges: Improvement in carrier transport Ieee Electron Device Letters. 34: 707-709. DOI: 10.1109/Led.2013.2253593 |
0.633 |
|
| 2013 |
Kumar V, Zheng L, Bakir M, Naeemi A. Compact modeling and optimization of fine-pitch interconnects for silicon interposers Proceedings of the 2013 Ieee International Interconnect Technology Conference, Iitc 2013. DOI: 10.1109/IITC.2013.6615571 |
0.557 |
|
| 2012 |
Rakheja S, Naeemi A. Graphene nanoribbon spin interconnects for nonlocal spin-torque circuits: Comparison of performance and energy per bit with CMOS interconnects Ieee Transactions On Electron Devices. 59: 51-59. DOI: 10.1109/Ted.2011.2171186 |
0.327 |
|
| 2012 |
Huang G, Bakir MS, Naeemi A, Meindl JD. Power delivery for 3-D chip stacks: Physical modeling and design implication Ieee Transactions On Components, Packaging and Manufacturing Technology. 2: 852-859. DOI: 10.1109/Tcpmt.2012.2185047 |
0.732 |
|
| 2011 |
Jamal O, Naeemi A. Ultralow-power single-wall carbon nanotube interconnects for subthreshold circuits Ieee Transactions On Nanotechnology. 10: 99-101. DOI: 10.1109/Tnano.2010.2095428 |
0.377 |
|
| 2011 |
Balakrishnan A, Naeemi A. Interconnect network analysis of many-core chips Ieee Transactions On Electron Devices. 58: 2831-2837. DOI: 10.1109/Ted.2011.2158104 |
0.309 |
|
| 2011 |
Rakheja S, Naeemi A. Modeling interconnects for post-CMOS devices and comparison with copper interconnects Ieee Transactions On Electron Devices. 58: 1319-1328. DOI: 10.1109/Ted.2011.2109004 |
0.349 |
|
| 2010 |
Rakheja S, Naeemi A. Interconnects for novel state variables: Performance modeling and device and circuit implications Ieee Transactions On Electron Devices. 57: 2711-2718. DOI: 10.1109/Ted.2010.2062186 |
0.336 |
|
| 2010 |
Balakrishnan A, Naeemi A. Optimal global interconnects for networks-on-chip in many-core architectures Ieee Electron Device Letters. 31: 290-292. DOI: 10.1109/Led.2010.2041319 |
0.383 |
|
| 2010 |
Meindl J, Naeemi A, Bakir M, Murali R. Nanoelectronics in retrospect, prospect and principle Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 53: 31-35. DOI: 10.1109/ISSCC.2010.5434062 |
0.684 |
|
| 2010 |
Rakheja S, Naeemi A, Meindl JD. Physical limitations on delay and energy dissipation of interconnects for post-CMOS devices 2010 Ieee International Interconnect Technology Conference, Iitc 2010. DOI: 10.1109/IITC.2010.5510448 |
0.483 |
|
| 2009 |
Naeemi A, Meindl JD. Carbon nanotube interconnects Annual Review of Materials Research. 39: 255-275. DOI: 10.1146/Annurev-Matsci-082908-145247 |
0.526 |
|
| 2009 |
Naeemi A, Meindl JD. Compact physics-based circuit models for graphene nanoribbon interconnects Ieee Transactions On Electron Devices. 56: 1822-1833. DOI: 10.1109/Ted.2009.2026122 |
0.557 |
|
| 2008 |
Naeemi A, Meindl JD. Performance modeling for single- and multiwall carbon nanotubes as signal and power interconnects in gigascale systems Ieee Transactions On Electron Devices. 55: 2574-2582. DOI: 10.1109/Ted.2008.2003028 |
0.575 |
|
| 2008 |
Naeemi A, Meindl JD. Electron transport modeling for junctions of zigzag and armchair graphene nanoribbons (GNRs) Ieee Electron Device Letters. 29: 497-499. DOI: 10.1109/Led.2008.920278 |
0.516 |
|
| 2008 |
Naeemi A, Meindl JD. Performance benchmarking for graphene nanoribbon, carbon Nanotube, and Cu interconnects 2008 Ieee International Interconnect Technology Conference, Iitc. 183-185. DOI: 10.1109/IITC.2008.4546961 |
0.472 |
|
| 2008 |
Naeemi A, Meindl JD. Physical models for electron transport in graphene nanoribbons and their junctions Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 400-405. DOI: 10.1109/ICCAD.2008.4681605 |
0.442 |
|
| 2008 |
Huang G, Naeemi A, Zhou T, O'Connor D, Muszynski A, Singh B, Becker D, Venuto J, Meindl JD. Compact physical models for chip and package power and ground distribution networks for gigascale integration (GSI) Proceedings - Electronic Components and Technology Conference. 646-651. DOI: 10.1109/ECTC.2008.4550040 |
0.544 |
|
| 2008 |
Bakir MS, King C, Sekar D, Thacker H, Dang B, Huang G, Naeemi A, Meindl JD. 3D heterogeneous integrated systems: Liquid cooling, power delivery, and implementation Proceedings of the Custom Integrated Circuits Conference. 663-670. DOI: 10.1109/CICC.2008.4672173 |
0.75 |
|
| 2008 |
Huang G, Sekar D, Naeemi A, Shakeri K, Meindl JD. Physical model for power supply noise and chip/package co-design in gigascale systems with the consideration of hot spots Proceedings of the Custom Integrated Circuits Conference. 841-844. DOI: 10.1109/CICC.2007.4405859 |
0.764 |
|
| 2008 |
Ni D, Lam T, Le Coz YL, Naeemi A, Meindl JD. Estimation of an RLC granularity metric for a CNT-bundle interconnect stack 2008 Proceedings - 25th International Vlsi Multilevel Interconnection Conference, Vmic 2008. 291-295. |
0.443 |
|
| 2007 |
Naeemi A, Meindl JD. Design and performance modeling for single-walled carbon nanotubes as local, semiglobal, and global interconnects in gigascale integrated systems Ieee Transactions On Electron Devices. 54: 26-37. DOI: 10.1109/Ted.2006.887210 |
0.612 |
|
| 2007 |
Naeemi A, Bakir MS. Chip-level and input/output interconnects for gigascale SOCs: Limits and opportunities 2006 Ieee International Systems-On-Chip Conference, Soc. 323-324. DOI: 10.1109/SOCC.2006.283908 |
0.516 |
|
| 2007 |
Naeemi A, Meindl JD. Conductance modeling for graphene nanoribbon (GNR) interconnects Ieee Electron Device Letters. 28: 428-431. DOI: 10.1109/Led.2007.895452 |
0.534 |
|
| 2007 |
Naeemi A, Meindl JD. Physical modeling of temperature coefficient of resistance for single- and multi-wall carbon nanotube interconnects Ieee Electron Device Letters. 28: 135-138. DOI: 10.1109/Led.2006.889240 |
0.529 |
|
| 2007 |
Sekar DC, Naeemi A, Sarvari R, Davis JA, Meindl JD. IntSim: A CAD tool for optimization of multilevel interconnect networks Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 560-567. DOI: 10.1109/ICCAD.2007.4397324 |
0.748 |
|
| 2007 |
Huang G, Bakir M, Naeemi A, Chen H, Meindl JD. Power delivery for 3D chip stacks: Physical modeling and design implication Ieee Topical Meeting On Electrical Performance of Electronic Packaging. 205-208. DOI: 10.1109/EPEP.2007.4387161 |
0.663 |
|
| 2007 |
Gang H, Sekar DC, Naeemi A, Shakeri K, Meindl JD. Compact physical models for power supply noise and chip/package co-design of gigascale integration Proceedings - Electronic Components and Technology Conference. 1659-1666. DOI: 10.1109/ECTC.2007.374017 |
0.766 |
|
| 2007 |
Naeemi A, Huang G, Meindl JD. Performance modeling for carbon nanotube interconnects in on-chip power distribution Proceedings - Electronic Components and Technology Conference. 420-428. DOI: 10.1109/ECTC.2007.373831 |
0.536 |
|
| 2007 |
Naeemi A, Sarvari R, Meindl JD. Performance modeling and optimization for single- and multi-wall carbon nanotube interconnects Proceedings - Design Automation Conference. 568-573. DOI: 10.1109/DAC.2007.375228 |
0.7 |
|
| 2007 |
Sarvari R, Naeemi A, Zarkesh-Ha P, Meindl JD. Design and optimization for nanoscale power distribution networks in gigascale systems Proceedings of the Ieee 2007 International Interconnect Technology Conference - Digest of Technical Papers. 190-192. |
0.775 |
|
| 2006 |
Naeemi A, Meindl JD. Compact physical models for multiwall carbon-nanotube interconnects Ieee Electron Device Letters. 27: 338-340. DOI: 10.1109/Led.2006.873765 |
0.545 |
|
| 2006 |
Naeemi A, Sarvari R, Meindl JD. On-chip interconnect networks at the end of the roadmap: Limits and nanotechnology opportunities 2006 International Interconnect Technology Conference, Iitc. 221-223. DOI: 10.1109/IITC.2006.1648693 |
0.698 |
|
| 2005 |
Mule AV, Villalaz RA, Joseph PJ, Naeemi A, Kohl PA, Gaylord TK, Meindl JD. Polylithic integration of electrical and optical interconnect technologies for gigascale fiber-to-the-chip communication Ieee Transactions On Advanced Packaging. 28: 421-433. DOI: 10.1109/Tadvp.2005.847838 |
0.537 |
|
| 2005 |
Naeemi A, Meindl JD. Monolayer metallic nanotube interconnects: Promising candidates for short local interconnects Ieee Electron Device Letters. 26: 544-546. DOI: 10.1109/Led.2005.852744 |
0.578 |
|
| 2005 |
Naeemi A, Meindl JD. Impact of electron-phonon scattering on the performance of carbon nanotube interconnects for GSI Ieee Electron Device Letters. 26: 476-478. DOI: 10.1109/Led.2005.851130 |
0.54 |
|
| 2005 |
Naeemi A, Sarvari R, Meindl JD. Performance comparison between carbon nanotube and copper interconnects for gigascale integration (GSI) Ieee Electron Device Letters. 26: 84-86. DOI: 10.1109/Led.2004.841440 |
0.72 |
|
| 2005 |
Naeemi A, Joshi Y, Fedorov A, Kohl P, Meindl JD. The urgency of deep sub-ambient cooling for gigascale integration 2005 International Conference On Integrated Circuit Design and Technology, Icicdt. 171-174. |
0.448 |
|
| 2005 |
Naeemi A, Meindl JD. Impact of deep sub-ambient cooling on GSI interconnect performance Proceedings of the Ieee 2005 International Interconnect Technology Conference, Iitc. 156-158. |
0.45 |
|
| 2005 |
Huang G, Naeemi A, Meindl JD. Minimizing energy-per-bit for On-board LC transmission lines Proceedings of the Ieee 2005 International Interconnect Technology Conference, Iitc. 77-79. |
0.43 |
|
| 2005 |
Sarvari R, Naeemi A, Venkatesan R, Meindl JD. Impact of size effects on the resistivity of copper wires and consequently the design and performance of metal interconnect networks Proceedings of the Ieee 2005 International Interconnect Technology Conference, Iitc. 197-199. |
0.693 |
|
| 2004 |
Naeemi A, Davis JA, Meindl JD. Compact physical models for multilevel interconnect crosstalk in gigascale integration (GSI) Ieee Transactions On Electron Devices. 51: 1902-1912. DOI: 10.1109/Ted.2004.837379 |
0.584 |
|
| 2004 |
Naeemi A, Davis JA, Meindl JD. Analysis and optimization of coplanar RLC lines for GSI global interconnection Ieee Transactions On Electron Devices. 51: 985-994. DOI: 10.1109/Ted.2004.829517 |
0.549 |
|
| 2004 |
Naeemi A, Meindl JD. An upper limit for aggregate I/O interconnect bandwidth of GSI chips constrained by power dissipation Proceedings of the Ieee 2004 International Interconnect Technology Conference. 157-159. |
0.491 |
|
| 2004 |
Sarvari R, Naeemi A, Meindl JD. General compact model for bit-rate limit of electrical interconnects considering DC resistance, skin effect and surface scattering Proceedings of the Ieee 2004 International Interconnect Technology Conference. 163-165. |
0.674 |
|
| 2004 |
Naeemi A, Sarvari R, Meindl JD. Performance comparison between carbon nanotube and copper interconnects for GSI Technical Digest - International Electron Devices Meeting, Iedm. 699-702. |
0.689 |
|
| 2003 |
Naeemi A, Venkatesan R, Meindl JD. Optimal global interconnects for GSI Ieee Transactions On Electron Devices. 50: 980-987. DOI: 10.1109/Ted.2003.812104 |
0.69 |
|
| 2002 |
Mule AV, Naeemi A, Glytsis EN, Gaylord TK, Meindl JD. Towards a comparison between chip-level optical interconnection and board-level exterconnection Proceedings of the Ieee 2002 International Interconnect Technology Conference, Iitc 2002. 92-94. DOI: 10.1109/IITC.2002.1014898 |
0.499 |
|
| 2002 |
Naeemi A, Venkatesan R, Meindl JD. System-on-a-chip global interconnect optimization Proceedings of the Annual Ieee International Asic Conference and Exhibit. 2002: 399-403. DOI: 10.1109/ASIC.2002.1158092 |
0.518 |
|
| 2001 |
Meindl JD, Venkatesan R, Davis JA, Joyner J, Naeemi A, Zarkesh-Ha P, Bakir M, Mulé T, Kohl PA, Martin KP. Interconnecting device opportunities for gigascale integration (GSI) Technical Digest - International Electron Devices Meeting. 525-528. |
0.769 |
|
| 2001 |
Naeemi A, Patel CS, Bakir MS, Zarkesh-Ha P, Martin KP, Meindl JD. Sea of leads: A disruptive paradigm for a system-on-a-chip (SoC) Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 280-281. |
0.743 |
|
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