Year |
Citation |
Score |
2018 |
Wang J, Wang Q, Jiang L, Li C, Liang X, Jing N. IBOM: An Integrated and Balanced On-Chip Memory for High Performance GPGPUs Ieee Transactions On Parallel and Distributed Systems. 29: 586-599. DOI: 10.1109/Tpds.2017.2773516 |
0.37 |
|
2018 |
Jiang L, Li T, Jing N, Kim NS, Guo M, Liang X. CNFET-Based High Throughput SIMD Architecture Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 37: 1331-1344. DOI: 10.1109/Tcad.2017.2695899 |
0.379 |
|
2017 |
Jing N, Jiang S, Chen S, Zhang J, Jiang L, Li C, Liang X. Bank Stealing for a Compact and Efficient Register File Architecture in GPGPU Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 25: 520-533. DOI: 10.1109/Tvlsi.2016.2584623 |
0.348 |
|
2016 |
Jing N, Jiang L, Zhang T, Li C, Fan F, Liang X. Energy-Efficient eDRAM-Based On-Chip Storage Architecture for GPGPUs Ieee Transactions On Computers. 65: 122-135. DOI: 10.1109/Tc.2015.2417545 |
0.384 |
|
2015 |
Zhang T, Jing N, Jiang K, Shu W, Wu MY, Liang X. Buddy SM: Sharing pipeline front-end for improved energy efficiency in GPGPUs Acm Transactions On Architecture and Code Optimization. 12. DOI: 10.1145/2744202 |
0.311 |
|
2009 |
Liang X, Wei G, Brooks D. Revival: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency Ieee Micro. 29: 127-138. DOI: 10.1109/Mm.2009.13 |
0.51 |
|
2008 |
Liang X, Canal R, Wei G, Brooks D. Replacing 6T SRAMs with 3T1D DRAMs in the L1 Data Cache to Combat Process Variability Ieee Micro. 28: 60-68. DOI: 10.1109/Mm.2008.12 |
0.514 |
|
Show low-probability matches. |