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S Simon Wong - Publications

Affiliations: 
Electrical Engineering Stanford University, Palo Alto, CA 
Website:
https://profiles.stanford.edu/s-simon-wong
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52 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2019 Jiang Z, Qin S, Li H, Fujii S, Lee D, Wong S, Wong H-P. Next-Generation Ultrahigh-Density 3-D Vertical Resistive Switching Memory (VRSM)—Part II: Design Guidelines for Device, Array, and Architecture Ieee Transactions On Electron Devices. 66: 5147-5154. DOI: 10.1109/Ted.2019.2950595  0.307
2017 Lee EH, Wong SS. Analysis and Design of a Passive Switched-Capacitor Matrix Multiplier for Approximate Computing Ieee Journal of Solid-State Circuits. 52: 261-271. DOI: 10.1109/Jssc.2016.2599536  0.3
2015 Zhang Z, Gao B, Fang Z, Wang X, Tang Y, Sohn J, Wong HP, Wong SS, Lo G. All-Metal-Nitride RRAM Devices Ieee Electron Device Letters. 36: 29-31. DOI: 10.1109/Led.2014.2367542  0.316
2015 Yeh CWS, Wong SS. Compact One-Transistor-N-RRAM Array Architecture for Advanced CMOS Technology Ieee Journal of Solid-State Circuits. DOI: 10.1109/Jssc.2015.2402217  0.333
2014 Fang Z, Wang XP, Sohn J, Weng BB, Zhang ZP, Chen ZX, Tang YZ, Lo GQ, Provine J, Wong SS, Wong HSP, Kwong DL. The role of ti capping layer in HfOx-Based RRAM Devices Ieee Electron Device Letters. 35: 912-914. DOI: 10.1109/Led.2014.2334311  0.312
2013 Park J, Oh S, Kim S, Wong HP, Wong SS. Impact of III–V and Ge Devices on Circuit Performance Ieee Transactions On Very Large Scale Integration Systems. 21: 1189-1200. DOI: 10.1109/Tvlsi.2012.2210450  0.306
2013 Zhang Z, Chen CY, Crnogorac F, Chen SL, Griffin PB, Pease RF, Plummer JD, Wong SS. Low-temperature monolithic three-layer 3-D process for FPGA Ieee Electron Device Letters. 34: 1044-1046. DOI: 10.1109/Led.2013.2266111  0.333
2013 Zhang Z, Wu Y, Wong H-P, Wong SS. Nanometer-Scale ${\rm HfO}_{x}$ RRAM Ieee Electron Device Letters. 34: 1005-1007. DOI: 10.1109/Led.2013.2265404  0.305
2011 Ou E, Wong SS. Array architecture for a nonvolatile 3-dimensional cross-point resistance-change memory Ieee Journal of Solid-State Circuits. 46: 2158-2170. DOI: 10.1109/Jssc.2011.2148430  0.312
2010 Crnogorac F, Wong S, Pease RFW. Semiconductor crystal islands for three-dimensional integration Journal of Vacuum Science & Technology. B. Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena. 28. DOI: 10.1116/1.3511473  0.316
2009 Lin YS, Wong SS. A 60-GHz low-noise amplifier for 60-GHz dual-conversion receiver Microwave and Optical Technology Letters. 51: 885-891. DOI: 10.1002/Mop.24200  0.301
2008 Nho H, Yoon SS, Wong SS, Jung SO. Numerical estimation of yield in sub-100-nm SRAM design using Monte Carlo simulation Ieee Transactions On Circuits and Systems Ii: Express Briefs. 55: 907-911. DOI: 10.1109/Tcsii.2008.923411  0.666
2008 Feng J, Thareja G, Kobayashi M, Chen S, Poon A, Bai Y, Griffin PB, Wong SS, Nishi Y, Plummer JD. High-performance gate-all-around GeOI p-MOSFETs fabricated by rapid melt growth using plasma nitridation and ALD Al2O3 gate dielectric and self-aligned NiGe contacts Ieee Electron Device Letters. 29: 805-807. DOI: 10.1109/Led.2008.2000613  0.303
2007 Lin M, Gamal AE, Lu Y, Wong S. Performance Benefits of Monolithically Stacked 3-D FPGA Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 216-229. DOI: 10.1109/Tcad.2006.887920  0.31
2007 Wang Z, Griffin PB, McVittie J, Wong S, McIntyre PC, Nishi Y. Resistive switching mechanism in ZNxCd1-xS nonvolatile memory devices Ieee Electron Device Letters. 28: 14-16. DOI: 10.1109/Led.2006.887640  0.316
2007 Reifenberg JP, Panzer MA, Kim S, Gibby AM, Zhang Y, Wong S, Wong HSP, Pop E, Goodson KE. Thickness and stoichiometry dependence of the thermal conductivity of GeSbTe films Applied Physics Letters. 91. DOI: 10.1063/1.2784169  0.699
2005 Talwalkar NA, Yue CP, Wong SS. Analysis and synthesis of on-chip spiral inductors Ieee Transactions On Electron Devices. 52: 176-182. DOI: 10.1109/Ted.2004.842535  0.664
2004 Lee H, Nix WD, Wong SS. Studies of the driving force for room-temperature microstructure evolution in electroplated copper films Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures. 22: 2369-2374. DOI: 10.1116/1.1788680  0.538
2004 Chang RT, Yang M, Ho PPC, Wang Y, Chia Y, Liew B, Yue CP, Wong SS. Modeling and optimization of substrate resistance for RF-CMOS Ieee Transactions On Electron Devices. 51: 421-426. DOI: 10.1109/Ted.2003.822586  0.319
2004 Talwalkar NA, Yue CP, Gan H, Wong SS. Integrated CMOS transmit-receive switch using LC-tuned substrate bias for 2.4-GHz and 5.2-GHz applications Ieee Journal of Solid-State Circuits. 39: 863-870. DOI: 10.1109/Jssc.2004.827809  0.671
2003 O'Mahony F, Yue CP, Horowitz MA, Wong SS. A 10-GHz global clock distribution using coupled standing-wave oscillators Ieee Journal of Solid-State Circuits. 38: 1813-1820. DOI: 10.1109/Jssc.2003.818299  0.727
2003 Chang RT, Talwalkar N, Yue P, Wong SS. Near speed-of-light signaling over on-chip electrical interconnects Ieee Journal of Solid-State Circuits. 38: 834-838. DOI: 10.1109/Jssc.2003.810060  0.668
2003 Lee H, Wong SS, Lopatin SD. Correlation of stress and texture evolution during self- and thermal annealing of electroplated Cu films Journal of Applied Physics. 93: 3796-3804. DOI: 10.1063/1.1555274  0.535
2002 Kleveland B, Diaz CH, Vook D, Madden L, Lee TH, Wong SS. Correction to "exploiting CMOS reverse interconnect scaling in multigigahertz amplifier and oscillator design" Ieee Journal of Solid-State Circuits. 37: 255-255. DOI: 10.1109/Jssc.2002.982433  0.704
2001 Kleveland B, Diaz CH, Vook D, Madden L, Lee TH, Wong SS. Exploiting CMOS reverse interconnect scaling in multigigahertz amplifier and oscillator design Ieee Journal of Solid-State Circuits. 36: 1480-1488. DOI: 10.1109/4.953476  0.732
2000 Kleveland B, Maloney TJ, Morgan I, Madden L, Lee TH, Wong SS. Distributed ESD protection for high-speed integrated circuits Ieee Electron Device Letters. 21: 390-392. DOI: 10.1109/55.852960  0.716
2000 Yue CP, Wong SS. Physical modeling of spiral inductors on silicon Ieee Transactions On Electron Devices. 47: 560-568. DOI: 10.1109/16.824729  0.312
1999 Wong SS, Ng SK, Lee HM. Vogt-Koyanagi-Harada disease: extensive vitiligo with prodromal generalized erythroderma. Dermatology (Basel, Switzerland). 198: 65-8. PMID 10026405  0.416
1999 Soh HT, Yue CP, McCarthy A, Ryu C, Lee TH, Wong SS, Quate CF. Ultra-Low Resistance, Through-Wafer Via (TWV) Technology and Its Applications in Three Dimensional Structures on Silicon Japanese Journal of Applied Physics. 38: 2393-2396. DOI: 10.1143/Jjap.38.2393  0.342
1998 Wong SS, Ryu C, Lee H, Kwon K. Barriers For Copper Interconnections Mrs Proceedings. 514: 75. DOI: 10.1557/Proc-514-75  0.505
1998 Asheghi M, Touzelbaev MN, Goodson KE, Leung YK, Wong SS. Temperature-Dependent Thermal Conductivity of Single-Crystal Silicon Layers in SOI Substrates Journal of Heat Transfer. 120: 30-36. DOI: 10.1115/1.2830059  0.332
1998 Leung Y, Paul AK, Plummer JD, Wong SS. Lateral IGBT in thin SOI for high voltage, high speed power IC Ieee Transactions On Electron Devices. 45: 2251-2254. DOI: 10.1109/16.725263  0.315
1998 Chan WWT, Sin JKO, Wong SS. A novel crosstalk isolation structure for bulk CMOS power IC's Ieee Transactions On Electron Devices. 45: 1580-1586. DOI: 10.1109/16.701492  0.304
1997 Chan ABY, Nguyen CT, Ko PK, Chan STH, Wong SS. Polished TFT's: surface roughness reduction and its correlation to device performance improvement Ieee Transactions On Electron Devices. 44: 455-463. DOI: 10.1109/16.556156  0.307
1997 Zetterling C, Östling M, Wongchotigul K, Spencer MG, Tang X, Harris CI, Nordell N, Wong SS. Investigation of aluminum nitride grown by metal–organic chemical-vapor deposition on silicon carbide Journal of Applied Physics. 82: 2990-2995. DOI: 10.1063/1.366136  0.326
1996 Zetterling C-, Wongchotigul K, Spencer MG, Harris CI, Wong SS, Östling M. Formation and High Frequency CV-Measurements of Aluminum / Aluminum Nitride / 6H Silicon Carbide Structures Mrs Proceedings. 423. DOI: 10.1557/Proc-423-667  0.338
1996 Chan WWT, Sin KO, Mok PKT, Wong SS. A power IC technology with excellent cross-talk isolation Ieee Electron Device Letters. 17: 467-469. DOI: 10.1109/55.537077  0.325
1995 Beiley M, Leung J, Wong SS. A Micromachined Array Probe Card-Characterization Ieee Transactions On Components Packaging and Manufacturing Technology Part B. 18: 184-191. DOI: 10.1109/96.365507  0.315
1995 Beiley M, Leung J, Wong SS. A Micromachined Array Probe Card—Fabrication Process Ieee Transactions On Components Packaging and Manufacturing Technology Part B. 18: 179-183. DOI: 10.1109/96.365506  0.321
1995 Racanelli M, Kuehne S, Huang WM, Wong S, Foerstner J, Hwang BY. Contact Technology for High Performance Scalable BiCMOS on TFSOI Ieee Electron Device Letters. 16: 424-426. DOI: 10.1109/55.464805  0.354
1995 Wong SS, Cho JS, Kang Hk, Ryu C. Reliability of chemically vapor deposited (CVD) copper interconnections Materials Chemistry &Amp; Physics. 41: 229-233. DOI: 10.1016/0254-0584(95)80034-4  0.325
1994 Nguyen CT, Kuehne SC, Garling LK, Wong SS, Drowley C. Application of Selective Epitaxial Silicon and Chemo-Mechanical Polishing to Bipolar Transistors Ieee Transactions On Electron Devices. 41: 2343-2350. DOI: 10.1109/16.337447  0.345
1994 Sakui K, Wong SS, Wooley BA. The Effects of Impact Ionization on the Operation of Neighboring Devices and Circuits Ieee Transactions On Electron Devices. 41: 1603-1607. DOI: 10.1109/16.310112  0.324
1993 Lee VV, Kuehne SC, Nguyen CT, Beiley MA, Wong SS. A selective CVD tungsten-strapped polysilicon local interconnection technology Ieee Transactions On Electron Devices. 40: 1223-1230. DOI: 10.1109/16.216425  0.306
1992 Thomas DC, Wong SS. A planar interconnection technology utilizing the selective deposition of tungsten-multilevel implementation Ieee Transactions On Electron Devices. 39: 901-907. DOI: 10.1109/16.127480  0.338
1991 Verdonckt-Vandebroek S, Wong SS, Woo JCS, Ko PK. High-gain lateral bipolar action in a MOSFET structure Ieee Transactions On Electron Devices. 38: 2487-2496. DOI: 10.1109/16.97413  0.303
1989 Sodini CG, Wong SS, Ko P. A framework to evaluate technology and device design enhancements for MOS integrated circuits Ieee Journal of Solid-State Circuits. 24: 118-127. DOI: 10.1109/4.16311  0.324
1987 Wong SS, Chen DC, Merchant P, Cass TR, Amano J, Chiu KY. HPSAC—A silicided amorphous-silicon contact and interconnect technology for VLSI Ieee Transactions On Electron Devices. 34: 587-592. DOI: 10.1109/T-Ed.1987.22967  0.329
1985 Wong SS, Oldham WG. Anodic nitridation of silicon and silicon dioxide Ieee Transactions On Electron Devices. 32: 978-982. DOI: 10.1109/T-Ed.1985.22056  0.598
1984 Wong SS, Oldham WG. A Multiwafer Plasma System for Anodic Nitridation and Oxidation Ieee Electron Device Letters. 5: 175-177. DOI: 10.1109/Edl.1984.25874  0.607
1983 Wong SS, Sodini CG, Ekstedt TW, Grinolds HR, Jackson KH, Kwan SH, Oldham WG. Low Pressure Nitrided‐Oxide as a Thin Gate Dielectric for MOSFET's Journal of the Electrochemical Society. 130: 1139-1144. DOI: 10.1149/1.2119904  0.559
1982 Sodini CG, Wong SS, Ekstedt TW, Grinolds HR, Oldham WG. IIA-5 a JMOS transistor fabricated with 100A low pressure nitrided-oxide gate dielectric Ieee Transactions On Electron Devices. 31: 17-21. DOI: 10.1109/T-Ed.1984.21468  0.604
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