| Year |
Citation |
Score |
| 2010 |
Irez K, Hu J, Zukowski CA. Characteristics of MS-CMOS logic in sub-32nm technologies Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 393-396. DOI: 10.1145/1785481.1785572 |
0.647 |
|
| 2006 |
Bastani A, Zukowski CA. A low-leakage high-speed monotonic static CMOS 64b adder in a dual gate oxide 65-nm CMOS technology Proceedings - International Symposium On Quality Electronic Design, Isqed. 312-317. DOI: 10.1109/ISQED.2006.12 |
0.647 |
|
| 2006 |
Bastani A, Zukowski CA. Monotonic static CMOS tradeoffs in sub-100nm technologies Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 2006: 278-283. |
0.668 |
|
| 2005 |
Chin P, Zukowski CA, Gristede GD, Kosonocky SV. Characterization of logic circuit techniques and optimization for high-leakage CMOS technologies Integration, the Vlsi Journal. 38: 491-504. DOI: 10.1016/j.vlsi.2004.07.011 |
0.565 |
|
| 2005 |
Bastani A, Zukowski CA. Characterization of monotonic static CMOS gates in a 65nm technology Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 408-411. |
0.668 |
|
| 2004 |
Bastani A, Zukowski CA. Design of superbuffers in sub-100nm CMOS technologies with significant gate leakage Proceedings of the Acm Great Lakes Symposium On Vlsi. 119-122. |
0.631 |
|
| 2004 |
Chin P, Zukowski CA, Gristede GD, Kosonocky S. Characterization of logic circuit techniques for high leakage CMOS technologies Proceedings of the Acm Great Lakes Symposium On Vlsi. 230-235. |
0.588 |
|
| 2000 |
Li SH, Zukowski CA. Application of dynamic power supply scaling in a low-energy ATM interface Proceedings - Ieee International Symposium On Circuits and Systems. 5: V-745-V-748. |
0.357 |
|
| 1999 |
Tretz C, Chuang CT, Terman L, Anderson C, Pelella M, Zukowski C. Metastability of SOI CMOS latches International Journal of Electronics. 86: 807-813. |
0.325 |
|
| 1998 |
Tretz C, Chuang CT, Terman L, Pelella M, Zukowski C. Performance comparison of differential static CMOS circuit topologies in SOI technology Ieee International Soi Conference. 123-124. |
0.458 |
|
| 1997 |
Tretz C, Chuang CT, Terman LM, Anderson CJ, Zukowski C. Metastability of SOI CMOS latches Ieee International Soi Conference. 162-163. |
0.481 |
|
| 1997 |
Zukowski CA, Wang SY. Use of selective precharge for low-power content-addressable memories Proceedings - Ieee International Symposium On Circuits and Systems. 3: 1788-1791. |
0.318 |
|
| 1996 |
Tretz C, Zukowski C. Conservative modeling of the contribution of spurious transitions to power dissipation in digital CMOS VLSI circuits Midwest Symposium On Circuits and Systems. 1: 317-320. |
0.322 |
|
| 1996 |
Tretz C, Ranganathan S, Zukowski C. Comparison of a wide range of differential CMOS logic topologies Midwest Symposium On Circuits and Systems. 1: 179-182. |
0.368 |
|
| 1994 |
Shi H, Ennis D, Fernandez S, Zukowski C, Wing O. VLSI design and cost analysis of broadband ATM switch elements Proceedings of the Annual Ieee International Asic Conference and Exhibit. 331-336. |
0.34 |
|
| 1993 |
Chen DP, Zukowski C, Banu M. Macromodeling BicMOS gates for circuit optimization Proceedings of the Custom Integrated Circuits Conference. 8.1.1-8.1.4. |
0.385 |
|
| 1993 |
Lin PS, Zukowski CA. Jitter due to signal history in digital logic circuits and its control strategies Proceedings - Ieee International Symposium On Circuits and Systems. 3: 2114-2117. |
0.323 |
|
| 1992 |
Pei TB, Zukowski C. High-Speed Parallel CRC Circuits in VLSI Ieee Transactions On Communications. 40: 653-657. DOI: 10.1109/26.141415 |
0.479 |
|
| 1991 |
Zukowski CA. High-Speed Data Transmission Using Low-Frequency Clocks Ieee Transactions On Circuits and Systems. 38: 273-280. DOI: 10.1109/31.101320 |
0.362 |
|
| 1991 |
Chen DP, Zukowski C. CMOS optimization including logic family mixing Proceedings - Ieee International Symposium On Circuits and Systems. 4: 2240-2243. |
0.419 |
|
| 1990 |
Monderer B, Pacifici G, Zukowski C. The cylinder switch: An architecture for a manageable VLSI giga-cell switch Conference Record - International Conference On Communications. 2: 567-571. |
0.361 |
|
| 1988 |
Zukowski C, Chen DP. Variable reduction in MOS timing models . 124-128. |
0.313 |
|
| 1986 |
Zukowski CA. BOUNDING APPROACH TO VLSI CIRCUIT SIMULATION Bounding Approach to Vlsi Circuit Simul. |
0.324 |
|
| 1985 |
Zukowski CA, Wyatt JL, Glasser LA. BOUNDING TECHNIQUES AND APPLICATIONS FOR VLSI CIRCUIT SIMULATION Proceedings - Ieee International Symposium On Circuits and Systems. 163-166. |
0.355 |
|
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