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John Wawrzynek - Publications

Affiliations: 
Electrical Engineering and Computer Science University of California, Berkeley, Berkeley, CA, United States 
Area:
Computer Architecture & Engineering (ARC)
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54 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2019 Dai G, Huang T, Wang Y, Yang H, Wawrzynek J. HyVE: Hy brid V ertex- E dge Memory Hierarchy for Energy-Efficient Graph Processing Ieee Transactions On Computers. 68: 1131-1146. DOI: 10.1109/Tc.2019.2893384  0.326
2016 Mor N, Zhang B, Kolb J, Chan DS, Goyal N, Sun N, Lutz K, Allman E, Wawrzynek J, Lee EA, Kubiatowicz J. Toward a Global Data Infrastructure Ieee Internet Computing. 20: 54-62. DOI: 10.1109/Mic.2016.51  0.384
2014 Cheng S, Wawrzynek J. Architectural synthesis of computational pipelines with decoupled memory access Proceedings of the 2014 International Conference On Field-Programmable Technology, Fpt 2014. 83-90. DOI: 10.1109/FPT.2014.7082758  0.471
2014 Lin M, Chen S, Demara RF, Wawrzynek J. ASTRO: Synthesizing application-specific reconfigurable hardware traces to exploit memory-level parallelism Microprocessors and Microsystems. 39: 553-564. DOI: 10.1016/J.Micpro.2015.03.005  0.453
2013 Lin M, Cheng S, Wawrzynek J. Extracting memory-level parallelism through reconfigurable hardware traces 2013 International Conference On Reconfigurable Computing and Fpgas, Reconfig 2013. DOI: 10.1109/ReConFig.2013.6732290  0.314
2012 Lin M, Bai Y, Wawrzynek J. Selectively fortifying reconfigurable computing device to achieve higher error resilience Journal of Electrical and Computer Engineering. DOI: 10.1155/2012/593532  0.43
2012 Lebedev I, Fletcher C, Cheng S, Martin J, Doupnik A, Burke D, Lin M, Wawrzynek J. Exploring many-core design templates for FPGAs and ASICs International Journal of Reconfigurable Computing. 2012. DOI: 10.1155/2012/439141  0.458
2012 Bachrach J, Vo H, Richards B, Lee Y, Waterman A, Avižienis R, Wawrzynek J, Asanović K. Chisel: Constructing hardware in a Scala embedded language Proceedings - Design Automation Conference. 1216-1225. DOI: 10.1145/2228360.2228584  0.656
2011 Fletcher CW, Lebedev IA, Asadi NB, Burke DR, Wawrzynek J. Bridging the GPGPU-FPGA efficiency gap Acm/Sigda International Symposium On Field Programmable Gate Arrays - Fpga. 119-122. DOI: 10.1145/1950413.1950439  0.424
2011 Lin M, Bai Y, Wawrzynek J. Discriminatively Fortified Computing with reconfigurable digital fabric Proceedings of Ieee International Symposium On High Assurance Systems Engineering. 112-119. DOI: 10.1109/HASE.2011.49  0.39
2010 Lin M, Lebedev I, Wawrzynek J. High-throughput Bayesian computing machine with reconfigurable hardware Acm/Sigda International Symposium On Field Programmable Gate Arrays - Fpga. 73-82. DOI: 10.1145/1723112.1723127  0.452
2010 Lin M, Wawrzynek J. Improving FPGA placement with dynamically adaptive stochastic tunneling Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 29: 1858-1869. DOI: 10.1109/Tcad.2010.2061670  0.397
2010 Lin M, Wawrzynek J, Gamal AE. Exploring FPGA routing architecture stochastically Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 29: 1509-1522. DOI: 10.1109/Tcad.2010.2061530  0.438
2010 Lin M, Cheng S, Wawrzynek J. Cascading deep pipelines to achieve high throughput in numerical reduction operations Proceedings - 2010 International Conference On Reconfigurable Computing and Fpgas, Reconfig 2010. 103-108. DOI: 10.1109/ReConFig.2010.70  0.381
2010 Lebedev I, Cheng S, Doupnik A, Martin J, Fletcher C, Burke D, Lin M, Wawrzynek J. MARC: A many-core approach to reconfigurable computing Proceedings - 2010 International Conference On Reconfigurable Computing and Fpgas, Reconfig 2010. 7-12. DOI: 10.1109/ReConFig.2010.49  0.478
2010 Lin M, Lebedev I, Wawrzynek J. OpenRCL: Low-power high-performance computing with reconfigurable devices Proceedings - 2010 International Conference On Field Programmable Logic and Applications, Fpl 2010. 458-463. DOI: 10.1109/FPL.2010.93  0.448
2009 Mohiyuddin M, Murphy M, Oliker L, Shalf J, Wawrzynek J, Williams S. A design methodology for domain-optimized power-efficient supercomputing Proceedings of the Conference On High Performance Computing Networking, Storage and Analysis, Sc '09. DOI: 10.1145/1654059.1654072  0.739
2009 Asanovic K, Bodik R, Demmel J, Keaveny T, Keutzer K, Kubiatowicz J, Morgan N, Patterson D, Sen K, Wawrzynek J, Wessel D, Yelick K. A view of the parallel computing landscape Communications of the Acm. 52: 56-67. DOI: 10.1145/1562764.1562783  0.668
2009 Markovsky Y, Patel Y, Wawrzynek J. Using adaptive routing to compensate for performance heterogeneity Proceedings - 2009 3rd Acm/Ieee International Symposium On Networks-On-Chip, Nocs 2009. 12-21. DOI: 10.1109/NOCS.2009.5071440  0.314
2008 Rabaey JM, Burke D, Lutz K, Wawrzynek J. Workloads of the future Ieee Design and Test of Computers. 25: 358-365. DOI: 10.1109/Mdt.2008.118  0.402
2008 DeHon A, Markovskiy Y, Caspi E, Chu M, Wawrzynek J, Huang R, Perissakis S, Pozzi L, Yeh J. Stream Computations Organized for Reconfigurable Execution Reconfigurable Computing. 203-218. DOI: 10.1016/B978-012370522-8.50014-5  0.712
2008 Richards BC, Chang C, Wawrzynek J, Brodersen RW. Programming Streaming FPGA Applications Using Block Diagrams in Simulink Reconfigurable Computing. 183-202. DOI: 10.1016/B978-012370522-8.50013-3  0.382
2007 Wawrzynek J, Patterson D, Oskin M, Lu SL, Kozyrakis C, Hoe JC, Chiou D, Asanović K. RAMP: Research accelerator for multiple processors Ieee Micro. 27: 46-57. DOI: 10.1109/Mm.2007.39  0.674
2007 Krasnov A, Schultz A, Wawrzynek J, Gibeling G, Droz PY. RAMP Blue: A message-passing manycore system in FPGAs Proceedings - 2007 International Conference On Field Programmable Logic and Applications, Fpl. 54-61. DOI: 10.1109/FPL.2007.4380625  0.381
2007 Wawrzynek J. Adventures with a reconfigurable research platform Proceedings - 2007 International Conference On Field Programmable Logic and Applications, Fpl. 3. DOI: 10.1109/FPL.2007.4380615  0.417
2006 DeHon A, Markovsky Y, Caspi E, Chu M, Huang R, Perissakis S, Pozzi L, Yeh J, Wawrzynek J. Stream computations organized for reconfigurable execution Microprocessors and Microsystems. 30: 334-354. DOI: 10.1016/J.Micpro.2006.02.009  0.762
2006 DeHon A, Huang R, Wawrzynek J. Stochastic spatial routing for reconfigurable networks Microprocessors and Microsystems. 30: 301-318. DOI: 10.1016/J.Micpro.2006.02.003  0.665
2005 Chang C, Wawrzynek J, Brodersen RW. BEE2: A high-end reconfigurable computing system Ieee Design and Test of Computers. 22: 114-125. DOI: 10.1109/Mdt.2005.30  0.523
2005 Chang C, Wawrzynek J, Droz PY, Brodersen RW. The design and application of a high-end reconfigurable computing system Proceedings of the 2005 International Conference On Engineering of Reconfigurable Systems and Algorithms, Ersa'05. 129-136.  0.421
2004 Weaver N, Hauser J, Wawrzynek J. The SFRA: A corner-turn FPGA architecture Acm/Sigda International Symposium On Field Programmable Gate Arrays - Fpga. 12: 3-12.  0.497
2003 Weaver N, Markovskiy Y, Patel Y, Wawrzynek J. Post-placement C-slow retiming for the xilinx virtex FPGA Acm/Sigda International Symposium On Field Programmable Gate Arrays - Fpga. 185-194.  0.731
2003 Huang R, Wawrzynek J, DeHon A. Stochastic, spatial routing for hypergraphs, trees, and meshes Acm/Sigda International Symposium On Field Programmable Gate Arrays - Fpga. 78-87.  0.337
2002 Weaver N, Wawrzynek J. The effects of datapath placement and C-slow retiming on three computational benchmarks, extended abstract Ieee Symposium On Fpgas For Custom Computing Machines, Proceedings. 2002: 303-304. DOI: 10.1109/FPGA.2002.1106694  0.308
2002 Dehon A, Huang R, Wawrzynek J. Hardware-assisted fast routing Ieee Symposium On Fpgas For Custom Computing Machines, Proceedings. 2002: 205-218. DOI: 10.1109/FPGA.2002.1106675  0.405
2002 Markovskiy Y, Caspi E, Huang R, Yeh J, Chu M, Wawrzynek J, DeHon A. Analysis of quasi-static scheduling techniques in a virtualized reconfigurable machine Acm/Sigda International Symposium On Field Programmable Gate Arrays - Fpga. 196-205.  0.745
2000 Callahan TJ, Hauser JR, Wawrzynek J. Garp architecture and C compiler Computer. 33: 62-69. DOI: 10.1109/2.839323  0.741
2000 Callahan TJ, Wawrzynek J. Adapting software pipelining for reconfigurable computing Proceedings of the International Conference On Compilers, Architecture and Synthesis For Embedded Systems. 57-64.  0.71
2000 Caspi E, Chu M, Huang R, Yeh J, Wawrzynek J, Dehon A. Stream computations organized for reconfigurable execution (Score) Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 1896: 605-614.  0.673
1999 DeHon A, Wawrzynek J. Reconfigurable computing: What, why, and implications for design automation Proceedings - Design Automation Conference. 610-615.  0.463
1999 Tsu W, Macy K, Joshi A, Huang R, Walker N, Tung T, Rowhani O, George V, Wawrzynek J, DeHon A. HSRA: High-speed, hierarchical synchronous reconfigurable array Acm/Sigda International Symposium On Field Programmable Gate Arrays - Fpga. 125-134.  0.396
1998 Callahan TJ, Chong P, DeHon A, Wawrzynek J. Fast module mapping and placement for datapaths in FPGAs Acm/Sigda International Symposium On Field Programmable Gate Arrays - Fpga. 123-132.  0.607
1998 Callahan TJ, Wawrzynek J. Instruction-level parallelism for reconfigurable computing Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 1482: 248-257.  0.676
1997 Lazzaro J, Wawrzynek J, Lippmann RP. A micropower analog circuit implementation of hidden Markov model state decoding Ieee Journal of Solid-State Circuits. 32: 1200-1209. DOI: 10.1109/4.604076  0.345
1997 Callahan TJ, Wawrzynek J. Datapath-oriented FPGA mapping and placement for configurable computing Ieee Symposium On Fpgas For Custom Computing Machines, Proceedings. 234-235.  0.664
1997 Hauser JR, Wawrzynek J. Garp: a MIPS processor with a reconfigurable coprocessor Ieee Symposium On Fpgas For Custom Computing Machines, Proceedings. 12-21.  0.552
1996 Wawrzynek J, Asanović K, Kingsbury B, Johnson D, Beck J, Morgan N. Spert-II: A Vector microprocessor system Computer. 29: 79-86. DOI: 10.1109/2.485896  0.494
1994 Lazzaro J, Wawrzynek J, Kramer A. Systems Technologies for Silicon Auditory Models Ieee Micro. 14: 7-15. DOI: 10.1109/40.285219  0.366
1994 Asanovic K, Beck J, Feldman J, Morgan N, Wawrzynek J. Supercomputer for neural computation Ieee International Conference On Neural Networks - Conference Proceedings. 1: 5-9.  0.62
1993 Lazzaro J, Wawrzynek J, Mahowald M, Sivilotti M, Gillespie D. Silicon auditory processors as computer peripherals. Ieee Transactions On Neural Networks / a Publication of the Ieee Neural Networks Council. 4: 523-8. PMID 18267754 DOI: 10.1109/72.217193  0.37
1993 Wawrzynek J, Asanovic K, Morgan N. The design of a neuro-microprocessor. Ieee Transactions On Neural Networks / a Publication of the Ieee Neural Networks Council. 4: 394-9. PMID 18267741 DOI: 10.1109/72.217180  0.658
1993 Asanović K, Beck J, Feldman J, Morgan N, Wawrzynek J. Designing a connectionist network supercomputer. International Journal of Neural Systems. 4: 317-26. PMID 8049794 DOI: 10.1142/S0129065793000250  0.645
1993 Asanović K, Morgan N, Wawrzynek J. Using simulations of reduced precision arithmetic to design a neuro-microprocessor Journal of Vlsi Signal Processing. 6: 33-44. DOI: 10.1007/BF01581957  0.579
1992 Asanovic K, Beck J, Kingsbury BED, Kohn P, Morgan N, Wawrzynek J. SPERT: A VLIW/SIMD microprocessor for artificial neural network computations Proceedings of the International Conference On Application. 178-190.  0.592
1991 Culler DE, Sah A, Schauser KE, von Eicken T, Wawrzynek J. Fine-grain parallelism with minimal hardware support. A compiler-controlled threaded abstract machine International Conference On Architectural Support For Programming Languages and Operating Systems - Asplos. 26: 164-175.  0.368
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