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Yun Chiu, Ph.D. - Publications

Affiliations: 
2004 University of California, Berkeley, Berkeley, CA, United States 
Area:
Design, Modeling and Analysis (DMA); Integrated Circuits (INC)
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39 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Li Y, Zhou Y, Chiu Y. A Compact Calibration Model for Linearizing CMOS Sample-and-Hold Circuits Ieee Transactions On Circuits and Systems Ii-Express Briefs. 1-1. DOI: 10.1109/Tcsii.2020.2977571  0.431
2019 Zhou Y, Xu B, Chiu Y. A 12-b 1-GS/s 31.5-mW Time-Interleaved SAR ADC With Analog HPF-Assisted Skew Calibration and Randomly Sampling Reference ADC Ieee Journal of Solid-State Circuits. 54: 2207-2218. DOI: 10.1109/Jssc.2019.2915583  0.655
2019 Xu H, Huang H, Cai Y, Du L, Zhou Y, Xu B, Gong D, Ye J, Chiu Y. A 78.5-dB SNDR Radiation- and Metastability-Tolerant Two-Step Split SAR ADC Operating Up to 75 MS/s With 24.9-mW Power Consumption in 65-nm CMOS Ieee Journal of Solid-State Circuits. 54: 441-451. DOI: 10.1109/Jssc.2018.2879942  0.563
2018 Wu B, Zhu S, Zhou Y, Chiu Y. A 9-bit 215 MS/s Folding-Flash Time-to-Digital Converter Based on Redundant Remainder Number System in 45-nm CMOS Ieee Journal of Solid-State Circuits. 53: 839-849. DOI: 10.1109/Jssc.2017.2782766  0.57
2018 Zhu S, Wu B, Cai Y, Chiu Y. A 2-GS/s 8-bit Non-Interleaved Time-Domain Flash ADC Based on Remainder Number System in 65-nm CMOS Ieee Journal of Solid-State Circuits. 53: 1172-1183. DOI: 10.1109/Jssc.2017.2774280  0.621
2017 Huang H, Xu H, Elies B, Chiu Y. A Non-Interleaved 12-b 330-MS/s Pipelined-SAR ADC With PVT-Stabilized Dynamic Amplifier Achieving Sub-1-dB SNDR Variation Ieee Journal of Solid-State Circuits. 52: 3235-3247. DOI: 10.1109/Jssc.2017.2732731  0.531
2017 Xu B, Zhou Y, Chiu Y. A 23-mW 24-GS/s 6-bit Voltage-Time Hybrid Time-Interleaved ADC in 28-nm CMOS Ieee Journal of Solid-State Circuits. 52: 1091-1100. DOI: 10.1109/Jssc.2016.2642204  0.66
2017 Naquin C, Cai Y, Hu G, Lee M, Chiu Y, Edwards H, Mathur G, Chatterjee T, Maggio K. Application of a Quantum-Well Silicon NMOS Transistor as a Folding Amplifier Frequency Multiplier Ieee Journal of the Electron Devices Society. 5: 224-231. DOI: 10.1109/Jeds.2017.2668362  0.397
2016 Huang H, Du L, Chiu Y. A 1.2-GS/s 8-bit two-step SAR ADC in 65-nm CMOS with passive residue transfer 2015 Ieee Asian Solid-State Circuits Conference, a-Sscc 2015 - Proceedings. DOI: 10.1109/Jssc.2017.2682839  0.478
2016 Wu B, Zhu S, Xu B, Chiu Y. A 24.7 mW 65 nm CMOS SAR-Assisted CT Δ Σ Modulator With Second-Order Noise Coupling Achieving 45 MHz Bandwidth and 75.3 dB SNDR Ieee Journal of Solid-State Circuits. DOI: 10.1109/Jssc.2016.2594953  0.563
2016 Zhu S, Xu B, Wu B, Soppimath K, Chiu Y. A Skew-Free 10 GS/s 6 bit CMOS ADC with Compact Time-Domain Signal Folding and Inherent DEM Ieee Journal of Solid-State Circuits. 51: 1785-1796. DOI: 10.1109/Jssc.2016.2558487  0.603
2016 Wu B, Zhu S, Xu B, Chiu Y. 15.1 A 24.7mW 45MHz-BW 75.3dB-SNDR SAR-assisted CT ΔΣ modulator with 2nd-order noise coupling in 65nm CMOS Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 59: 270-271. DOI: 10.1109/ISSCC.2016.7418011  0.426
2015 Xu B, Chiu Y. Comprehensive Background Calibration of Time-Interleaved Analog-to-Digital Converters Ieee Transactions On Circuits and Systems. 62: 1306-1314. DOI: 10.1109/Tcsi.2015.2403035  0.595
2015 Sarkar S, Zhou Y, Elies B, Chiu Y. PN-Assisted Deterministic Digital Background Calibration of Multistage Split-Pipelined ADC Ieee Transactions On Circuits and Systems. 62: 654-661. DOI: 10.1109/Tcsi.2014.2373032  0.594
2015 Wu B, Chiu Y. A 40 nm CMOS derivative-free if Active-RC BPF with programmable bandwidth and center frequency achieving over 30 dBm IIP3 Ieee Journal of Solid-State Circuits. 50: 1772-1784. DOI: 10.1109/Jssc.2015.2412953  0.545
2015 Zhou Y, Xu B, Chiu Y. A 12 bit 160 MS/s Two-Step SAR ADC With Background Bit-Weight Calibration Using a Time-Domain Proximity Detector Ieee Journal of Solid-State Circuits. 50: 920-931. DOI: 10.1109/Jssc.2014.2384025  0.646
2015 Xu H, Zhou Y, Chiu Y, Gong D, Liu T, Ye J. High-speed, high-resolution, radiation-tolerant SAR ADCs for particle physics experiments Journal of Instrumentation. 10. DOI: 10.1088/1748-0221/10/04/C04035  0.499
2015 Zhou Y, Chiu Y. Digital calibration of inter-stage nonlinear errors in pipelined SAR ADCs Analog Integrated Circuits and Signal Processing. 82: 533-542. DOI: 10.1007/S10470-015-0493-3  0.643
2014 Wang G, Kacani F, Chiu Y. IRD Digital Background Calibration of SAR ADC With Coarse Reference ADC Acceleration Ieee Transactions On Circuits and Systems Ii-Express Briefs. 61: 11-15. DOI: 10.1109/Tcsii.2013.2291051  0.581
2014 Lee S, Chiu Y. A 15-MHz Bandwidth 1-0 MASH $\Sigma \Delta $ ADC With Nonlinear Memory Error Calibration Achieving 85-dBc SFDR Ieee Journal of Solid-State Circuits. 49: 695-707. DOI: 10.1109/Jssc.2014.2304364  0.616
2013 Xu H, Gong D, Chiu Y. A Comparative Study of Amplitude and Timing Estimation in Experimental Particle Physics using Monte Carlo Simulation Journal of Modern Physics. 4: 42-47. DOI: 10.4236/Jmp.2013.45B009  0.326
2013 Chiu Y. On the Operation of CMOS Active-Cascode Gain Stage Journal of Computational Chemistry. 1: 18-24. DOI: 10.4236/Jcc.2013.16004  0.433
2012 Hoyos S, Tsang CW, Vanderhaegen J, Chiu Y, Aibara Y, Khorramabadi H, Nikolic B. A 15 MHz to 600 MHz, 20 mW, 0.38 mm 2 split-control, fast coarse locking digital DLL in 0.13 μ m CMOS Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 20: 564-568. DOI: 10.1109/Tvlsi.2011.2106170  0.519
2012 Liu W, Chiu Y. Time-Interleaved Analog-to-Digital Conversion With Online Adaptive Equalization Ieee Transactions On Circuits and Systems. 59: 1384-1395. DOI: 10.1109/Tcsi.2011.2177005  0.568
2011 Lee S, Chiu Y. Digital Calibration of Capacitor Mismatch in Sigma-Delta Modulators Ieee Transactions On Circuits and Systems. 58: 690-698. DOI: 10.1109/Tcsi.2010.2073870  0.511
2011 Chiu Y. Equalization techniques for nonlinear analog circuits Ieee Communications Magazine. 49: 132-139. DOI: 10.1109/Mcom.2011.5741157  0.508
2011 Liu W, Huang P, Chiu Y. A 12-bit, 45-MS/s, 3-mW Redundant Successive-Approximation-Register Analog-to-Digital Converter With Digital Calibration Ieee Journal of Solid-State Circuits. 46: 2661-2672. DOI: 10.1109/Jssc.2011.2163556  0.594
2011 Huang P, Hsien S, Lu V, Wan P, Lee S, Liu W, Chen B, Lee Y, Chen W, Yang T, Ma G, Chiu Y. SHA-Less Pipelined ADC With In Situ Background Clock-Skew Calibration Ieee Journal of Solid-State Circuits. 46: 1893-1903. DOI: 10.1109/Jssc.2011.2151510  0.598
2010 Peng B, Li H, Lin P, Chiu Y. An Offset Double Conversion Technique for Digital Calibration of Pipelined ADCs Ieee Transactions On Circuits and Systems Ii: Express Briefs. 57: 961-965. DOI: 10.1109/Tcsii.2010.2087990  0.55
2010 Peng B, Li H, Lee S, Lin P, Chiu Y. A Virtual-ADC Digital Background Calibration Technique for Multistage A/D Conversion Ieee Transactions On Circuits and Systems Ii-Express Briefs. 57: 853-857. DOI: 10.1109/Tcsii.2010.2082850  0.563
2010 Kwon DH, Li H, Chang Y, Tseng R, Chiu Y. Digitally Equalized CMOS Transmitter Front-End With Integrated Power Amplifier Ieee Journal of Solid-State Circuits. 45: 1602-1614. DOI: 10.1109/Jssc.2010.2048140  0.553
2009 Li H, Kwon DH, Chen D, Chiu Y. A Fast Digital Predistortion Algorithm for Radio-Frequency Power Amplifier Linearization With Loop Delay Compensation Ieee Journal of Selected Topics in Signal Processing. 3: 374-383. DOI: 10.1109/Jstsp.2009.2020562  0.466
2009 Liu W, Chiu Y. Background digital calibration of successive approximation adc with adaptive equalisation Electronics Letters. 45: 456-458. DOI: 10.1049/El.2009.2374  0.507
2008 Tseng R, Poon ASY, Chiu Y. A Mixed-Signal Vector Modulator for Eigenbeamforming Receivers Ieee Transactions On Circuits and Systems Ii-Express Briefs. 55: 479-483. DOI: 10.1109/Tcsii.2007.912732  0.478
2008 Huang P, Chiu Y. Calibration of sampling clock skew in SHA-less pipeline ADCs Electronics Letters. 44: 1061-1062. DOI: 10.1049/El:20081966  0.424
2004 Chiu Y, Tsang CW, Nikolić B, Gray PR. Least mean square adaptive digital background calibration of pipelined analog-to-digital converters Ieee Transactions On Circuits and Systems I: Regular Papers. 51: 38-46. DOI: 10.1109/Tcsi.2003.821306  0.655
2004 Chiu Y, Gray PR, Nikolić B. A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR Ieee Journal of Solid-State Circuits. 39: 2139-2151. DOI: 10.1109/Jssc.2004.836232  0.698
2000 Chiu Y. Inherently linear capacitor error-averaging techniques for pipelined a/d conversion Ieee Transactions On Circuits and Systems Ii: Analog and Digital Signal Processing. 47: 229-232. DOI: 10.1109/82.826750  0.564
1999 Chiu Y, Jalali B, Garner S, Steier W. Broad-band electronic linearizer for externally modulated analog fiber-optic links Ieee Photonics Technology Letters. 11: 48-50. DOI: 10.1109/68.736386  0.44
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