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Keshab K. Parhi - Publications

Affiliations: 
Electrical Engineering University of Minnesota, Twin Cities, Minneapolis, MN 
Area:
Electronics and Electrical Engineering, Computer Science
Website:
https://cse.umn.edu/ece/keshab-parhi
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244 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2021 Chu SH, Parhi KK, Westlund Schreiner M, Lenglet C, Mueller BA, Klimes-Dougan B, Cullen KR. Effect of SSRIs on Resting-State Functional Brain Networks in Adolescents with Major Depressive Disorder. Journal of Clinical Medicine. 10. PMID 34640340 DOI: 10.3390/jcm10194322  0.684
2020 Liu X, Parhi KK. Molecular and DNA Artificial Neural Networks via Fractional Coding. Ieee Transactions On Biomedical Circuits and Systems. PMID 32149654 DOI: 10.1109/Tbcas.2020.2979485  0.35
2020 Avvaru SVS, Zeng Z, Parhi KK. Homogeneous and Heterogeneous Feed-Forward XOR Physical Unclonable Functions Ieee Transactions On Information Forensics and Security. 15: 2485-2498. DOI: 10.1109/Tifs.2020.2968113  0.342
2020 Zhang Q, Chen Y, Li S, Zeng X, Parhi KK. A High-Performance Stochastic LDPC Decoder Architecture Designed via Correlation Analysis Ieee Transactions On Circuits and Systems I-Regular Papers. 1-14. DOI: 10.1109/Tcsi.2020.3003457  0.453
2020 Cheng C, Parhi KK. Fast 2D Convolution Algorithms for Convolutional Neural Networks Ieee Transactions On Circuits and Systems I: Regular Papers. 67: 1678-1691. DOI: 10.1109/Tcsi.2020.2964748  0.417
2020 Ge L, Parhi KK. Classification Using Hyperdimensional Computing: A Review Ieee Circuits and Systems Magazine. 20: 30-47. DOI: 10.1109/Mcas.2020.2988388  0.372
2019 Sen B, Chu SH, Parhi KK. Ranking Regions, Edges and Classifying Tasks in Functional Brain Graphs by Sub-Graph Entropy. Scientific Reports. 9: 7628. PMID 31110317 DOI: 10.1038/S41598-019-44103-8  0.592
2019 Koteshwara S, Das A, Parhi KK. Architecture Optimization and Performance Comparison of Nonce-Misuse-Resistant Authenticated Encryption Algorithms Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 27: 1053-1066. DOI: 10.1109/Tvlsi.2019.2894656  0.401
2019 Zhang Z, Parhi KK. MUSE: Minimum Uncertainty and Sample Elimination Based Binary Feature Selection Ieee Transactions On Knowledge and Data Engineering. 31: 1750-1764. DOI: 10.1109/Tkde.2018.2865778  0.308
2019 Parhi KK, Liu Y. Computing Arithmetic Functions Using Stochastic Logic by Series Expansion Ieee Transactions On Emerging Topics in Computing. 7: 44-59. DOI: 10.1109/Tetc.2016.2618750  0.398
2019 Zhang Z, Parhi KK. M3U: Minimum Mean Minimum Uncertainty Feature Selection for Multiclass Classification Journal of Signal Processing Systems. 92: 9-22. DOI: 10.1007/S11265-019-1443-6  0.322
2019 Govindan V, Koteshwara S, Das A, Parhi KK, Chakraborty RS. ProTro: A Probabilistic Counter Based Hardware Trojan Attack on FPGA Based MACSec Enabled Ethernet Switch Space. 159-175. DOI: 10.1007/978-3-030-35869-3_12  0.339
2018 Chu SH, Lenglet C, Schreiner MW, Klimes-Dougan B, Cullen K, Parhi KK. Anatomical Biomarkers for Adolescent Major Depressive Disorder from Diffusion Weighted Imaging using SVM Classifier. Conference Proceedings : ... Annual International Conference of the Ieee Engineering in Medicine and Biology Society. Ieee Engineering in Medicine and Biology Society. Annual Conference. 2018: 2740-2743. PMID 30440968 DOI: 10.1109/EMBC.2018.8512852  0.694
2018 Chu SH, Lenglet C, Schreiner MW, Klimes-Dougan B, Cullen K, Parhi KK. Biomarkers for Adolescent MDD from Anatomical Connectivity and Network Topology Using Diffusion MRI. Conference Proceedings : ... Annual International Conference of the Ieee Engineering in Medicine and Biology Society. Ieee Engineering in Medicine and Biology Society. Annual Conference. 2018: 1152-1155. PMID 30440595 DOI: 10.1109/EMBC.2018.8512505  0.683
2018 Chu SH, Lenglet C, Schreiner MW, Klimes-Dougan B, Cullen K, Parhi KK. Classifying Treated vs. Untreated MDD Adolescents from Anatomical Connectivity using Nonlinear SVM. Conference Proceedings : ... Annual International Conference of the Ieee Engineering in Medicine and Biology Society. Ieee Engineering in Medicine and Biology Society. Annual Conference. 2018: 1-4. PMID 30440303 DOI: 10.1109/EMBC.2018.8513168  0.686
2018 Salehi SA, Liu X, Riedel MD, Parhi KK. Computing Mathematical Functions using DNA via Fractional Coding. Scientific Reports. 8: 8312. PMID 29844537 DOI: 10.1038/S41598-018-26709-6  0.335
2018 Chu SH, Parhi KK, Lenglet C. Function-specific and Enhanced Brain Structural Connectivity Mapping via Joint Modeling of Diffusion and Functional MRI. Scientific Reports. 8: 4741. PMID 29549287 DOI: 10.1038/S41598-018-23051-9  0.707
2018 Koteshwara S, Kim CH, Parhi KK. Key-Based Dynamic Functional Obfuscation of Integrated Circuits Using Sequentially Triggered Mode-Based Design Ieee Transactions On Information Forensics and Security. 13: 79-93. DOI: 10.1109/Tifs.2017.2738600  0.396
2018 Parhi KK. Stochastic Logic Implementations of Polynomials With All Positive Coefficients by Expansion Methods Ieee Transactions On Circuits and Systems Ii: Express Briefs. 65: 1698-1702. DOI: 10.1109/Tcsii.2017.2756862  0.375
2018 Garrido M, Unnikrishnan NK, Parhi KK. A Serial Commutator Fast Fourier Transform Architecture for Real-Valued Signals Ieee Transactions On Circuits and Systems Ii: Express Briefs. 65: 1693-1697. DOI: 10.1109/Tcsii.2017.2753941  0.408
2018 Koteshwara S, Parhi KK. Incremental-Precision Based Feature Computation and Multi-Level Classification for Low-Energy Internet-of-Things Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 8: 822-835. DOI: 10.1109/Jetcas.2018.2836319  0.394
2017 Rashno A, Nazari B, Koozekanani DD, Drayna PM, Sadri S, Rabbani H, Parhi KK. Fully-automated segmentation of fluid regions in exudative age-related macular degeneration subjects: Kernel graph cut in neutrosophic domain. Plos One. 12: e0186949. PMID 29059257 DOI: 10.1371/Journal.Pone.0186949  0.3
2017 Rashno A, Koozekanani DD, Drayna PM, Nazari B, Sadri S, Rabbani H, Parhi KK. Fully-Automated Segmentation of Fluid/Cyst Regions in Optical Coherence Tomography Images with Diabetic Macular Edema using Neutrosophic Sets and Graph Algorithms. Ieee Transactions On Bio-Medical Engineering. PMID 28783619 DOI: 10.1109/Tbme.2017.2734058  0.343
2017 Lao Y, Parhi KK. Canonic FFT flow graphs for real-valued even/odd symmetric inputs Eurasip Journal On Advances in Signal Processing. 2017. DOI: 10.1186/S13634-017-0477-9  0.386
2017 Liu Y, Parhi KK. Computing Polynomials Using Unipolar Stochastic Logic Acm Journal On Emerging Technologies in Computing Systems. 13: 1-30. DOI: 10.1145/3007648  0.414
2017 Yuan B, Parhi KK. VLSI Architectures for the Restricted Boltzmann Machine Acm Journal On Emerging Technologies in Computing Systems. 13: 35. DOI: 10.1145/3007193  0.545
2017 Yuan B, Parhi KK. LLR-Based Successive-Cancellation List Decoder for Polar Codes With Multibit Decision Ieee Transactions On Circuits and Systems Ii: Express Briefs. 64: 21-25. DOI: 10.1109/Tcsii.2016.2546904  0.543
2017 Lao Y, Yuan B, Kim CH, Parhi KK. Reliable PUF-Based Local Authentication With Self-Correction Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 36: 201-213. DOI: 10.1109/Tcad.2016.2569581  0.526
2017 Lao Y, Parhi KK. Canonic Composite Length Real-Valued FFT Journal of Signal Processing Systems. 90: 1401-1414. DOI: 10.1007/S11265-017-1296-9  0.357
2017 Liu Y, Parhi KK. Linear-Phase Lattice FIR Digital Filter Architectures Using Stochastic Logic Journal of Signal Processing Systems. 90: 791-803. DOI: 10.1007/S11265-017-1224-Z  0.363
2016 Salehi SA, Parhi KK, Riedel MD. Chemical Reaction Networks for Computing Polynomials. Acs Synthetic Biology. PMID 27598466 DOI: 10.1021/Acssynbio.5B00163  0.354
2016 Lao Y, Tang Q, Kim CH, Parhi KK. Beat Frequency Detector--Based High-Speed True Random Number Generators Acm Journal On Emerging Technologies in Computing Systems. 13: 1-25. DOI: 10.1145/2866574  0.382
2016 Liu Y, Parhi KK. Architectures for Recursive Digital Filters Using Stochastic Computing Ieee Transactions On Signal Processing. 64: 3705-3718. DOI: 10.1109/Tsp.2016.2552513  0.372
2016 Wang Y, Yuan B, Parhi KK. Improved BER Performance With Rotated Head Array and 2-D Detector in Two-Dimensional Magnetic Recording Ieee Transactions On Magnetics. 52: 1-6. DOI: 10.1109/Tmag.2015.2513381  0.465
2016 Liu Y, Parhi KK. Architectures for stochastic normalized and modified lattice IIR filters Conference Record - Asilomar Conference On Signals, Systems and Computers. 2016: 1351-1358. DOI: 10.1109/ACSSC.2015.7421363  0.324
2016 Lao Y, Parhi KK. Canonic real-valued radix-2n FFT computations Conference Record - Asilomar Conference On Signals, Systems and Computers. 2016: 441-446. DOI: 10.1109/ACSSC.2015.7421166  0.303
2015 Zhang Z, Parhi KK. Low-Complexity Seizure Prediction From iEEG/sEEG Using Spectral Power and Ratios of Spectral Power. Ieee Transactions On Biomedical Circuits and Systems. PMID 26529783 DOI: 10.1109/Tbcas.2015.2477264  0.325
2015 Yuan B, Parhi KK. Reduced-latency LLR-based SC list decoder for polar codes Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 20: 107-110. DOI: 10.1145/2742060.2742108  0.314
2015 Chu SH, Lenglet C, Parhi KK. Joint brain connectivity estimation from diffusion and functional MRI data Proceedings of Spie. 9413: 941321. DOI: 10.1117/12.2082346  0.708
2015 Yuan B, Parhi KK. Low-Latency Successive-Cancellation List Decoders for Polar Codes with Multibit Decision Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 23: 2268-2280. DOI: 10.1109/Tvlsi.2014.2359793  0.534
2015 Lao Y, Parhi KK. Obfuscating DSP circuits via high-level transformations Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 23: 819-830. DOI: 10.1109/Tvlsi.2014.2323976  0.391
2015 Salehi SA, Jiang H, Riedel MD, Parhi KK. Molecular Sensing and Computing Systems Ieee Transactions On Molecular, Biological and Multi-Scale Communications. 1: 249-264. DOI: 10.1109/Tmbmc.2016.2537301  0.452
2015 Chinnapalanichamy A, Parhi KK. Serial and interleaved architectures for computing real FFT Icassp, Ieee International Conference On Acoustics, Speech and Signal Processing - Proceedings. 2015: 1066-1070. DOI: 10.1109/ICASSP.2015.7178133  0.309
2015 Yuan B, Parhi KK. Algorithm and architecture for hybrid decoding of polar codes Conference Record - Asilomar Conference On Signals, Systems and Computers. 2015: 2050-2053. DOI: 10.1109/ACSSC.2014.7094833  0.301
2015 Yuan B, Parhi KK. Successive cancellation list polar decoder using log-likelihood ratios Conference Record - Asilomar Conference On Signals, Systems and Computers. 2015: 548-552. DOI: 10.1109/ACSSC.2014.7094505  0.36
2014 Yuan B, Parhi KK. Early stopping criteria for energy-efficient low-latency belief-propagation polar code decoders Ieee Transactions On Signal Processing. 62: 6496-6506. DOI: 10.1109/Tsp.2014.2366712  0.508
2014 Wang Y, Yuan B, Parhi KK, Victora RH. Two-Dimensional Magnetic Recording Using a Rotated Head Array and LDPC Code Decoding Ieee Transactions On Magnetics. 50: 1-4. DOI: 10.1109/Tmag.2014.2321147  0.438
2014 Zhang C, Parhi KK. Latency Analysis and Architecture Design of Simplified SC Polar Decoders Ieee Transactions On Circuits and Systems Ii: Express Briefs. 61: 115-119. DOI: 10.1109/Tcsii.2013.2291065  0.383
2014 Yuan B, Parhi KK. Low-latency successive-cancellation polar decoder architectures using 2-bit decoding Ieee Transactions On Circuits and Systems I: Regular Papers. 61: 1241-1254. DOI: 10.1109/Tcsi.2013.2283779  0.552
2014 Parhi KK, Ayinala M. Low-complexity welch power spectral density computation Ieee Transactions On Circuits and Systems I: Regular Papers. 61: 172-182. DOI: 10.1109/Tcsi.2013.2264711  0.817
2014 Lao Y, Parhi KK. Statistical analysis of MUX-based physical unclonable functions Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 33: 649-662. DOI: 10.1109/Tcad.2013.2296525  0.34
2014 Lao Y, Parhi KK. Protecting DSP circuits through obfuscation Proceedings - Ieee International Symposium On Circuits and Systems. 798-801. DOI: 10.1109/ISCAS.2014.6865256  0.313
2014 Zhang C, Parhi KK. Interleaved successive cancellation polar decoders Proceedings - Ieee International Symposium On Circuits and Systems. 401-404. DOI: 10.1109/ISCAS.2014.6865150  0.312
2014 Yuan B, Parhi KK. Architectures for polar BP decoders using folding Proceedings - Ieee International Symposium On Circuits and Systems. 205-208. DOI: 10.1109/ISCAS.2014.6865101  0.333
2013 Jiang H, Salehi SA, Riedel MD, Parhi KK. Discrete-time signal processing with DNA. Acs Synthetic Biology. 2: 245-54. PMID 23654264 DOI: 10.1021/Sb300087N  0.448
2013 Kharam A, Jiang H, Riedel M, Parhi K. Binary counting with chemical reactions. Pacific Symposium On Biocomputing. Pacific Symposium On Biocomputing. 302-13. PMID 21121058 DOI: 10.1142/9789814335058_0032  0.337
2013 Kung TL, Parhi KK. Optimized joint timing synchronization and channel estimation for communications systems with multiple transmit antennas Eurasip Journal On Advances in Signal Processing. 2013. DOI: 10.1186/1687-6180-2013-139  0.318
2013 Kung TL, Parhi KK. Performance evaluation of variable transmission rate OFDM systems via network source coding Eurasip Journal On Advances in Signal Processing. 2013: 1-16. DOI: 10.1186/1687-6180-2013-12  0.367
2013 Kung TL, Parhi KK. Semiblind frequency-domain timing synchronization and channel estimation for OFDM systems Eurasip Journal On Advances in Signal Processing. 2013. DOI: 10.1186/1687-6180-2013-1  0.371
2013 Parhi KK. Comments on Low-energy CSMT carry generators and binary adders Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 21: 791. DOI: 10.1109/Tvlsi.2012.2190771  0.342
2013 Zhang C, Parhi KK. Low-Latency Sequential and Overlapped Architectures for Successive Cancellation Polar Decoder Ieee Transactions On Signal Processing. 61: 2429-2441. DOI: 10.1109/Tsp.2013.2251339  0.446
2013 Ayinala M, Lao Y, Parhi KK. An in-place fft architecture for real-valued signals Ieee Transactions On Circuits and Systems Ii: Express Briefs. 60: 652-656. DOI: 10.1109/Tcsii.2013.2273841  0.825
2013 Parhi KK. Hierarchical folding and synthesis of iterative data flow graphs Ieee Transactions On Circuits and Systems Ii: Express Briefs. 60: 597-601. DOI: 10.1109/Tcsii.2013.2268658  0.356
2013 Salehi SA, Amirfattahi R, Parhi KK. Pipelined architectures for real-valued FFT and hermitian-symmetric IFFT with real datapaths Ieee Transactions On Circuits and Systems Ii: Express Briefs. 60: 507-511. DOI: 10.1109/Tcsii.2013.2268411  0.425
2013 Ayinala M, Parhi KK. FFT architectures for real-valued signals based on radix-23 and Radix-24 algorithms Ieee Transactions On Circuits and Systems I: Regular Papers. 60: 2422-2430. DOI: 10.1109/Tcsi.2013.2246251  0.829
2013 Jiang H, Riedel MD, Parhi KK. Digital logic with molecular reactions Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 721-727. DOI: 10.1109/ICCAD.2013.6691194  0.41
2013 Yuan B, Parhi KK. Architecture optimizations for BP polar decoders Icassp, Ieee International Conference On Acoustics, Speech and Signal Processing - Proceedings. 2654-2658. DOI: 10.1109/ICASSP.2013.6638137  0.309
2013 Ayinala M, Parhi KK. Low-energy architectures for Support Vector Machine computation Conference Record - Asilomar Conference On Signals, Systems and Computers. 2167-2171. DOI: 10.1109/ACSSC.2013.6810693  0.815
2012 Ayinala M, Parhi KK. Low complexity algorithm for seizure prediction using Adaboost. Conference Proceedings : ... Annual International Conference of the Ieee Engineering in Medicine and Biology Society. Ieee Engineering in Medicine and Biology Society. Annual Conference. 2012: 1061-4. PMID 23366078 DOI: 10.1109/EMBC.2012.6346117  0.786
2012 Ayinala M, Parhi KK. Parallel pipelined FFT architectures with reduced number of delays Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 63-66. DOI: 10.1145/2206781.2206798  0.82
2012 Kung TL, Parhi KK. Optimized joint timing synchronization and channel estimation for OFDM systems Ieee Wireless Communications Letters. 1: 149-152. DOI: 10.1109/Wcl.2012.022812.120015  0.618
2012 Ayinala M, Brown M, Parhi KK. Pipelined parallel FFT architectures via folding transformation Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 20: 1068-1081. DOI: 10.1109/Tvlsi.2011.2147338  0.824
2012 Zhang C, Parhi KK. A Network-Efficient Nonbinary QC-LDPC Decoder Architecture Ieee Transactions On Circuits and Systems I: Regular Papers. 59: 1359-1371. DOI: 10.1109/Tcsi.2011.2177001  0.431
2012 Jiang H, Riedel MD, Parhi KK. Digital signal processing with molecular reactions Ieee Design and Test of Computers. 29: 21-31. DOI: 10.1109/Mdt.2012.2192144  0.467
2012 Cohen AE, Lin JH, Parhi KK. Variable data rate (VDR) network congestion control (NCC) applied to voice/audio communication Computer Networks. 56: 1343-1356. DOI: 10.1016/J.Comnet.2011.12.009  0.673
2011 Park Y, Luo L, Parhi KK, Netoff T. Seizure prediction with spectral power of EEG using cost-sensitive support vector machines. Epilepsia. 52: 1761-70. PMID 21692794 DOI: 10.1115/1.3455144  0.309
2011 Ayinala M, Parhi KK. High-speed parallel architectures for linear feedback shift registers Ieee Transactions On Signal Processing. 59: 4459-4469. DOI: 10.1109/Tsp.2011.2159495  0.832
2011 Cohen AE, Parhi KK. Secure variable data rate transmission Ieee Transactions On Circuits and Systems Ii: Express Briefs. 58: 100-104. DOI: 10.1109/Tcsii.2011.2106313  0.561
2011 Cohen AE, Parhi KK. Architecture optimizations for the RSA public key cryptosystem: A tutorial Ieee Circuits and Systems Magazine. 11: 24-34. DOI: 10.1109/Mcas.2011.942747  0.663
2011 Liu R, Parhi KK. Power reduction in frequency-selective FIR filters under voltage overscaling Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 1: 343-356. DOI: 10.1109/Jetcas.2011.2165749  0.636
2011 Kung TL, Parhi KK. Frequency domain symbol synchronization for OFDM systems Ieee International Conference On Electro Information Technology. DOI: 10.1109/EIT.2011.5978592  0.585
2011 Jiang H, Riedel MD, Parhi KK. Asynchronous computation with molecular reactions Conference Record - Asilomar Conference On Signals, Systems and Computers. 493-497. DOI: 10.1109/ACSSC.2011.6190049  0.409
2010 Liu Y, Zhang T, Parhi KK. Computation Error Analysis in Digital Signal Processing Systems With Overscaled Supply Voltage Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 18: 517-526. DOI: 10.1109/Tvlsi.2009.2012863  0.398
2010 Oh D, Parhi KK. Low-complexity switch network for reconfigurable LDPC decoders Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 18: 85-94. DOI: 10.1109/Tvlsi.2008.2007736  0.664
2010 Oh D, Parhi KK. Min-Sum Decoder Architectures With Reduced Word Length for LDPC Codes Ieee Transactions On Circuits and Systems I-Regular Papers. 57: 105-115. DOI: 10.1109/Tcsi.2009.2016171  0.444
2010 Ayinala M, Parhi KK. Efficient parallel VLSI architecture for linear feedback shift registers Ieee Workshop On Signal Processing Systems, Sips: Design and Implementation. 52-57. DOI: 10.1109/SIPS.2010.5624764  0.832
2010 Ayinala M, Parhi KK. Parallel-pipelined radix-22 FFT architecture for real valued signals Conference Record - Asilomar Conference On Signals, Systems and Computers. 1274-1278. DOI: 10.1109/ACSSC.2010.5757736  0.823
2009 Saberinia E, Tang J, Tewfik A, Parhi K. Pulsed-OFDM Modulation for Ultrawideband Communications Ieee Transactions On Vehicular Technology. 58: 720-726. DOI: 10.1109/Tvt.2008.923680  0.444
2009 Cohen AE, Parhi KK. A low-complexity hybrid LDPC code encoder for IEEE 802.3an (10GBase-T) ethernet Ieee Transactions On Signal Processing. 57: 4085-4094. DOI: 10.1109/Tsp.2009.2022919  0.657
2009 Garrido M, Parhi K, Grajal J. A Pipelined FFT Architecture for Real-Valued Signals Ieee Transactions On Circuits and Systems I: Regular Papers. 56: 2634-2643. DOI: 10.1109/Tcsi.2009.2017125  0.499
2009 Liu R, Parhi KK. Low-latency low-complexity architectures for viterbi decoders Ieee Transactions On Circuits and Systems I: Regular Papers. 56: 2315-2324. DOI: 10.1109/Tcsi.2008.2012217  0.667
2009 Chen J, Gu Y, Parhi KK. Novel FEXT Cancellation and Equalization for High Speed Ethernet Transmission Ieee Transactions On Circuits and Systems. 56: 1272-1285. DOI: 10.1109/Tcsi.2008.2008479  0.588
2009 Park CS, Parhi KK, Park S. Probabilistic Spherical Detection and VLSI Implementation for Multiple-Antenna Systems Ieee Transactions On Circuits and Systems. 56: 685-698. DOI: 10.1109/Tcsi.2008.2002544  0.428
2009 Cheng C, Parhi KK. High speed VLSI architecture for general linear feedback shift register (LFSR) structures Conference Record - Asilomar Conference On Signals, Systems and Computers. 713-717. DOI: 10.1109/ACSSC.2009.5469943  0.378
2009 Oh D, Parhi KK. Low complexity decoder architecture for low-density parity-check codes Journal of Signal Processing Systems. 56: 217-228. DOI: 10.1007/s11265-008-0231-5  0.341
2009 Ma J, Parhi KK. On pipelined implementations of QRD-RLS adaptive filters Qrd-Rls Adaptive Filtering. 269-297. DOI: 10.1007/978-0-387-09734-3_10  0.337
2008 Oh D, Parhi KK. Nonuniformly quantized min-sum decoder architecture for low-density parity-check codes Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 451-456. DOI: 10.1145/1366110.1366217  0.302
2008 Liu R, Parhi KK. Fast composite field S-Box architectures for Advanced Encryption Standard Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 65-70. DOI: 10.1145/1366110.1366128  0.329
2008 Cheng C, Parhi KK. High-speed VLSI implementation of 2-D discrete wavelet transform Ieee Transactions On Signal Processing. 56: 393-403. DOI: 10.1109/Tsp.2007.900754  0.436
2008 Cheng C, Parhi KK. Hardware Efficient Low-Latency Architecture for High Throughput Rate Viterbi Decoders Ieee Transactions On Circuits and Systems Ii: Express Briefs. 55: 1254-1258. DOI: 10.1109/Tcsii.2008.2008061  0.358
2008 Gu Y, Parhi KK. Design of parallel Tomlinson-Harashima precoders Ieee Transactions On Circuits and Systems Ii: Express Briefs. 55: 447-451. DOI: 10.1109/Tcsii.2007.914435  0.562
2008 Chen J, Gu Y, Parhi KK. Low-Complexity Echo and NEXT Cancellers for High-Speed Ethernet Transceivers Ieee Transactions On Circuits and Systems. 55: 2827-2840. DOI: 10.1109/Tcsi.2008.920085  0.607
2008 Liu R, Parhi KK. Minimal complexity low-latency architectures for Viterbi decoders Ieee Workshop On Signal Processing Systems, Sips: Design and Implementation. 140-145. DOI: 10.1109/SIPS.2008.4671752  0.311
2008 Oh D, Parhi KK. Area efficient controller design of barrel shifters for reconfigurable LDPC decoders Proceedings - Ieee International Symposium On Circuits and Systems. 240-243. DOI: 10.1109/ISCAS.2008.4541399  0.366
2008 Chen J, Parhi KK. New stable IIR modeling of long FIR filters with Low complexity Conference Record - Asilomar Conference On Signals, Systems and Computers. 1649-1653. DOI: 10.1109/ACSSC.2008.5074704  0.31
2007 Gu Y, Parhi KK. Pipelined Parallel Decision-Feedback Decoders for High-Speed Ethernet Over Copper Ieee Transactions On Signal Processing. 55: 707-715. DOI: 10.1109/Tsp.2006.885776  0.62
2007 Cheng C, Parhi KK. High-Throughput VLSI Architecture for FFT Computation Ieee Transactions On Circuits and Systems Ii: Express Briefs. 54: 863-867. DOI: 10.1109/Tcsii.2007.901635  0.421
2007 Cho K, Park J, Kim B, Chung J, Parhi KK. Design of a Sample-Rate Converter From CD to DAT Using Fractional Delay Allpass Filter Ieee Transactions On Circuits and Systems Ii: Express Briefs. 54: 19-23. DOI: 10.1109/Tcsii.2006.885067  0.358
2007 Gu Y, Parhi KK. High-speed architecture design of Tomlinson-Harashima precoders Ieee Transactions On Circuits and Systems I: Regular Papers. 54: 1929-1937. DOI: 10.1109/Tcsi.2007.904688  0.564
2007 Cheng C, Parhi KK. Low-cost fast VLSI algorithm for discrete fourier transform Ieee Transactions On Circuits and Systems I: Regular Papers. 54: 791-806. DOI: 10.1109/Tcsi.2006.888772  0.431
2007 Cheng C, Parhi KK. Low- Cost Parallel FIR Filter Structures With 2-Stage Parallelism Ieee Transactions On Circuits and Systems I: Regular Papers. 54: 280-290. DOI: 10.1109/Tcsi.2006.885976  0.39
2007 Oh D, Parhi KK. Performance of quantized min-sum decoding algorithms for irregular LDPC codes Proceedings - Ieee International Symposium On Circuits and Systems. 2758-2761.  0.31
2007 Zhang Y, Parhi KK. Parallel architecture of list sphere decoders Proceedings - Ieee International Symposium On Circuits and Systems. 2096-2099.  0.301
2006 Cheng C, Parhi KK. Hardware efficient fast DCT based on novel cyclic convolution structures Ieee Transactions On Signal Processing. 54: 4419-4434. DOI: 10.1109/Tsp.2006.881269  0.485
2006 Lin JH, Parhi KK. Parallelization of context-based adaptive binary arithmetic coders Ieee Transactions On Signal Processing. 54: 3702-3711. DOI: 10.1109/Tsp.2006.879298  0.645
2006 Zhang X, Parhi KK. On the optimum constructions of composite field for the AES algorithm Ieee Transactions On Circuits and Systems Ii: Express Briefs. 53: 1153-1157. DOI: 10.1109/Tcsii.2006.882217  0.554
2006 Cheng C, Parhi KK. High-speed parallel CRC implementation based on unfolding, pipelining, and retiming Ieee Transactions On Circuits and Systems Ii: Express Briefs. 53: 1017-1021. DOI: 10.1109/Tcsii.2006.882213  0.466
2006 Oh D, Parhi KK. Low complexity implementations of sum-product algorithm for decoding low-density parity-check codes 2006 Ieee Workshop On Signal Processing Systems Design and Implementation, Sips. 262-267. DOI: 10.1109/SIPS.2006.352592  0.368
2006 Oh D, Parhi KK. Low complexity design of high speed parallel decision feedback equalizers Proceedings of the International Conference On Application-Specific Systems, Architectures and Processors. 118-122. DOI: 10.1109/ASAP.2006.43  0.373
2006 Cheng C, Parhi KK. Erratum to: Hardware efficient fast computation of the discrete fourier transform Journal of Vlsi Signal Processing Systems For Signal, Image and Video Technology. 43: 105-106. DOI: 10.1007/S11265-006-8456-7  0.319
2006 Gao L, Parhi KK. Models for architectural power and power grid noise analysis on data bus Journal of Vlsi Signal Processing Systems For Signal, Image, and Video Technology. 44: 25-46. DOI: 10.1007/s11265-006-4176-2  0.47
2006 Lin JH, Parhi KK. Low complexity block turbo equalization Proceedings - Ieee International Symposium On Circuits and Systems. 5091-5094.  0.363
2005 Zhang X, Parhi KK. High-speed architectures for parallel long BCH encoders Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 13: 872-877. DOI: 10.1109/Tvlsi.2005.850125  0.605
2005 Parhi KK. Design of multigigabit multiplexer-loop-based decision feedback equalizers Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 13: 489-493. DOI: 10.1109/Tvlsi.2004.842935  0.397
2005 Cheng C, Parhi KK. A novel systolic array structure for DCT Ieee Transactions On Circuits and Systems Ii-Express Briefs. 52: 366-369. DOI: 10.1109/Tcsii.2005.850432  0.408
2005 Lin JH, Parhi KK. VLSI architectures for stereoscopic video disparity matching and object extraction Proceedings - Ieee International Symposium On Circuits and Systems. 2373-2376. DOI: 10.1109/ISCAS.2005.1465102  0.325
2005 Chen Y, Parhi KK. On the performance and implementation issues of interleaved single parity check turbo product codes Journal of Vlsi Signal Processing Systems For Signal, Image, and Video Technology. 39: 35-47. DOI: 10.1023/B:VLSI.0000047270.49225.52  0.308
2005 Shanbhag N, Parhi K. Guest Editorial The Journal of Vlsi Signal Processing-Systems For Signal, Image, and Video Technology. 39: 5-6. DOI: 10.1023/B:VLSI.0000047267.81368.52  0.483
2005 Chao C, Parhi KK. Low cost parallel adaptive filter structures Conference Record - Asilomar Conference On Signals, Systems and Computers. 2005: 354-358.  0.325
2004 Sundararajan V, Sapatnekar SS, Parhi KK. A new approach for integration of min-area retiming and min-delay padding for simultaneously addressing short-path and long-path constraints Acm Transactions On Design Automation of Electronic Systems (Todaes). 9: 273-289. DOI: 10.1145/1013948.1013949  0.344
2004 Zhang X, Parhi KK. Fast factorization architecture in soft-decision reed-solomon decoding Ieee Workshop On Signal Processing Systems, Sips: Design and Implementation. 101-106. DOI: 10.1109/Tvlsi.2004.842914  0.607
2004 Zhang X, Parhi KK. High-speed VLSI architectures for the AES algorithm Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 12: 957-967. DOI: 10.1109/Tvlsi.2004.832943  0.652
2004 Kong JJ, Parhi KK. Low-latency architectures for high-throughput rate Viterbi decoders Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 12: 642-651. DOI: 10.1109/Tvlsi.2004.827600  0.607
2004 Chen Y, Parhi KK. Small area parallel chien search architectures for long BCH codes Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 12: 545-549. DOI: 10.1109/Tvlsi.2004.826203  0.444
2004 Cho K, Lee K, Chung J, Parhi KK. Design of low-error fixed-width modified booth multiplier Ieee Transactions On Very Large Scale Integration Systems. 12: 522-531. DOI: 10.1109/Tvlsi.2004.825853  0.336
2004 Ma J, Parhi KK. Pipelined CORDIC-based state-space orthogonal recursive digital filters using matrix look-ahead Ieee Transactions On Signal Processing. 52: 2102-2119. DOI: 10.1109/Tsp.2004.828947  0.401
2004 Zhang T, Parhi K. Joint<tex>$(3, k)$</tex>-Regular LDPC Code and Decoder/Encoder Design Ieee Transactions On Signal Processing. 52: 1065-1079. DOI: 10.1109/Tsp.2004.823508  0.396
2004 Cheng C, Parhi KK. Hardware efficient fast parallel FIR filter structures based on iterated short convolution Proceedings - Ieee International Symposium On Circuits and Systems. 3. DOI: 10.1109/Tcsi.2004.832784  0.417
2004 Chen Y, Parhi KK. Overlapped message passing for quasi-cyclic low-density parity check codes Ieee Transactions On Circuits and Systems I: Regular Papers. 51: 1106-1113. DOI: 10.1109/Tcsi.2004.826194  0.392
2004 Parhi KK. An improved pipelined MSB-first add-compare select unit structure for Viterbi decoders Ieee Transactions On Circuits and Systems I: Regular Papers. 51: 504-511. DOI: 10.1109/Tcsi.2004.823657  0.406
2004 Parhi KK. Eliminating the fanout bottleneck in parallel long BCH encoders Ieee Transactions On Circuits and Systems I: Regular Papers. 51: 512-516. DOI: 10.1109/Tcsi.2004.823655  0.425
2004 Chi Z, Wang Z, Parhi K. On the Better Protection of Short-Frame Turbo Codes Ieee Transactions On Communications. 52: 1435-1439. DOI: 10.1109/Tcomm.2004.833144  0.661
2004 Chi Z, Song L, Parhi K. On The Performance/Complexity Tradeoff in Block Turbo Decoder Design Ieee Transactions On Communications. 52: 173-175. DOI: 10.1109/Tcomm.2003.822728  0.574
2004 Parhi KK. Pipelining of parallel multiplexer loops and decision feedback equalizers Icassp, Ieee International Conference On Acoustics, Speech and Signal Processing - Proceedings. 5.  0.301
2004 Kong JJ, Parhi KK. Quantum convolutional codes design and their encoder architectures Conference Record - Asilomar Conference On Signals, Systems and Computers. 1: 1131-1135.  0.453
2004 Gu Y, Parhi KK. Parallel design for parallel decision feedback decoders for 10GBASE-T Midwest Symposium On Circuits and Systems. 2.  0.304
2003 Kong JJ, Parhi KK. Interleaved convolutional code and its Viterbi decoder architecture Eurasip Journal On Applied Signal Processing. 2003: 1328-1334. DOI: 10.1155/S1110865703309126  0.582
2003 Chen Y, Parhi KK. Low-Complexity Decoding of Block Turbo-Coded System with Antenna Diversity Eurasip Journal On Advances in Signal Processing. 2003. DOI: 10.1155/S1110865703305116  0.399
2003 Zhang T, Parhi KK. An FPGA implementation of (3,6)-regular low-density parity-check code decoder Eurasip Journal On Applied Signal Processing. 2003: 530-542. DOI: 10.1155/S1110865703212105  0.429
2003 Sundararajan V, Parhi K. Synthesis of minimum-area folded architectures for rectangular multidimensional multirate DSP systems Ieee Transactions On Signal Processing. 51: 1954-1965. DOI: 10.1109/Tsp.2003.810289  0.488
2003 Kim S, Chung J, Parhi KK. Low error fixed-width CSD multiplier with efficient sign extension Ieee Transactions On Circuits and Systems Ii: Analog and Digital Signal Processing. 50: 984-993. DOI: 10.1109/Tcsii.2003.820231  0.513
2003 Chang YN, Parhi KK. An efficient pipelined FFT architecture Ieee Transactions On Circuits and Systems Ii: Analog and Digital Signal Processing. 50: 322-325. DOI: 10.1109/Tcsii.2003.811439  0.474
2003 Wang Z, Parhi KK. High performance, high throughput turbo/SOVA decoder design Ieee Transactions On Communications. 51: 570-579. DOI: 10.1109/Tcomm.2003.810832  0.638
2003 Kong JJ, Parhi KK. K-nested layered look-ahead method and architectures for high throughput Viterbi decoder Ieee Workshop On Signal Processing Systems, Sips: Design and Implementation. 2003: 99-104. DOI: 10.1109/SIPS.2003.1235651  0.543
2003 Kong JJ, Parhi KK. Interleaved cyclic redundancy check (CRC) code Conference Record of the Asilomar Conference On Signals, Systems and Computers. 2: 2137-2141.  0.506
2002 Chung JG, Parhi KK. Frequency spectrum based low-area low-power parallel FIR filter design Eurasip Journal On Applied Signal Processing. 2002: 944-953. DOI: 10.1155/S1110865702205077  0.396
2002 Kuhlmann M, Parhi KK. P-CORDIC: A precomputation based rotation CORDIC algorithm Eurasip Journal On Applied Signal Processing. 2002: 936-943. DOI: 10.1155/S1110865702205028  0.371
2002 Wang Z, Chi Z, Parhi KK. Area-efficient high-speed decoding schemes for turbo decoders Ieee Transactions On Very Large Scale Integration Systems. 10: 902-912. DOI: 10.1109/Tvlsi.2002.808451  0.704
2002 Wang Z, Parhi KK. On-line extraction of soft decoding information and applications in VLSI turbo decoding Ieee Transactions On Circuits and Systems Ii: Analog and Digital Signal Processing. 49: 760-769. DOI: 10.1109/Tcsii.2002.807759  0.57
2002 Parhi KK, Shanbhag NR. Message from the workshop chairs Ieee Workshop On Signal Processing Systems, Sips: Design and Implementation. 2002: iii. DOI: 10.1109/SIPS.2002.1049674  0.512
2002 Xinmiao Z, Parhi KK. Implementation approaches for the advanced encryption standard algorithm Ieee Circuits and Systems Magazine. 2: 24-46. DOI: 10.1109/Mcas.2002.1173133  0.399
2002 Sundararajan V, Sapatnekar S, Parhi K. Fast and exact transistor sizing based on iterative relaxation Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 21: 568-581. DOI: 10.1109/43.998628  0.326
2002 Dhaou IB, Parhi KK, Tenhunen H. Energy Efficient Signaling in Deep-submicron Technology Vlsi Design. 15: 563-586. DOI: 10.1080/1065514021000012192  0.356
2002 Freking WL, Parhi KK. Performance-scalable array architectures for modular multiplication Journal of Vlsi Signal Processing Systems For Signal, Image, and Video Technology. 31: 101-116. DOI: 10.1023/A:1015337204517  0.794
2002 Chi Z, Parhi KK. High speed VLSI architecture design for block turbo decoder Proceedings - Ieee International Symposium On Circuits and Systems. 1.  0.588
2002 Chi Z, Parhi KK. High speed algorithm and VLSI architecture design for decoding BCH product codes Icassp, Ieee International Conference On Acoustics, Speech and Signal Processing - Proceedings. 3.  0.582
2002 Chen Y, Parhi KK. A very low complexity soft decoding of space-time block codes Icassp, Ieee International Conference On Acoustics, Speech and Signal Processing - Proceedings. 3.  0.305
2002 Kong JJ, Parhi KK. Viterbi decoder architecture for interleaved convolutional code Conference Record of the Asilomar Conference On Signals, Systems and Computers. 2: 1934-1937.  0.505
2001 Kuhlmann M, Parhi KK. Novel low-power shared division and square-root architecture using the GST algorithm Vlsi Design. 12: 365-376. DOI: 10.1155/2001/51413  0.407
2001 Gao L, Parhi KK. Custom VLSI design of efficient low latency and low power finite field multiplier for Reed-Solomon codec Materials Research Society Symposium - Proceedings. 626. DOI: 10.1109/ISCAS.2001.922302  0.524
2001 Chi Z, Ma J, Parhi KK. Hybrid annihilation transformation (HAT) for pipelining QRD-based least-square adaptive filters Ieee Transactions On Circuits and Systems Ii: Analog and Digital Signal Processing. 48: 661-674. DOI: 10.1109/82.958336  0.592
2001 Parhi KK. Approaches to low-power implementations of DSP systems Ieee Transactions On Circuits and Systems I: Fundamental Theory and Applications. 48: 1214-1224. DOI: 10.1109/81.956016  0.384
2001 Ma J, Parhi KK, Deprettere EF. A unified algebraic transformation approach for parallel recursive and adaptive filtering and SVD algorithms Ieee Transactions On Signal Processing. 49: 424-437. DOI: 10.1109/78.902125  0.451
2001 Zhang T, Parhi KK. Systematic design of original and modified Mastrovito multipliers for general irreducible polynomials Ieee Transactions On Computers. 50: 734-749. DOI: 10.1109/12.936239  0.442
2001 Zervakis M, Sundararajan V, Parhi K. Vector processing of wavelet coefficients for robust image denoising Image and Vision Computing. 19: 435-450. DOI: 10.1016/S0262-8856(00)00089-5  0.376
2001 Zhang T, Parhi KK. Joint code and decoder design for implementation-oriented (3, k)-regular LDPC codes Conference Record of the Asilomar Conference On Signals, Systems and Computers. 2: 1232-1236.  0.303
2001 Gao L, Parhi KK. Models for power consumption and power grid noise due to datapath transition activity Proceedings of the Ieee Great Lakes Symposium On Vlsi. 121-126.  0.468
2001 Chen Y, Parhi KK. A very low complexity block turbo decoder composed of extended Hamming codes Conference Record / Ieee Global Telecommunications Conference. 1: 171-175.  0.343
2000 Song L, Parhi K, Kuroda I, Nishitani T. Hardware/software codesign of finite field datapath for low-energy Reed-Solomon codecs Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 8: 160-172. DOI: 10.1109/92.831436  0.396
2000 Gao L, Parhi KK. Hierarchical pipelining and folding of QRD-RLS adaptive filters and its application to digital beamforming Ieee Transactions On Circuits and Systems Ii: Analog and Digital Signal Processing. 47: 1503-1519. DOI: 10.1109/82.899644  0.614
2000 Deprettere E, Parhi K, Ma J. Pipelined CORDIC-based cascade orthogonal IIR digital filters Ieee Transactions On Circuits and Systems Ii: Analog and Digital Signal Processing. 47: 1238-1253. DOI: 10.1109/82.885131  0.387
2000 Chang YN, Parhi KK. High-performance digit-serial complex multiplier Ieee Transactions On Circuits and Systems Ii: Analog and Digital Signal Processing. 47: 570-572. DOI: 10.1109/82.847078  0.454
2000 Chung J, Kim H, Parhi KK. Angle-constrained IIR filter pipelining for reduced coefficient sensitivities Ieee Transactions On Circuits and Systems Ii: Analog and Digital Signal Processing. 47: 555-559. DOI: 10.1109/82.847073  0.374
2000 Ma J, Parhi KK, Hekstra GJ, Deprettere EF. Efficient implementations of pipelined CORDIC based IIR digital filters using fast orthonormal /spl mu/-rotations Ieee Transactions On Signal Processing. 48: 2712-2716. DOI: 10.1109/78.863093  0.395
2000 Satyanarayana JH, Parhi KK. Power Estimation of Digital Data Paths Using HEAT Ieee Design and Test of Computers. 17: 101-110. DOI: 10.1109/54.844339  0.302
2000 Chang Y, Suzuki H, Parhi KK. A 2-Mb/s 256-state 10-mW rate-1/3 Viterbi decoder Ieee Journal of Solid-State Circuits. 35: 826-834. DOI: 10.1109/4.845186  0.406
2000 Shalash AF, Parhi KK. Power efficient folding of pipelined LMS adaptive filters with applications to wireline digital communications Journal of Vlsi Signal Processing Systems For Signal, Image, and Video Technology. 25: 199-213. DOI: 10.1023/A:1008131306000  0.313
2000 Freking WL, Parhi KK. Modular multiplication in the residue number system with application to massively-parallel public-key cryptography systems Conference Record of the Asilomar Conference On Signals, Systems and Computers. 2: 1339-1343.  0.776
2000 Freking RA, Parhi KK. Low-memory, fixed-latency Huffman encoder for unbounded-length codes Conference Record of the Asilomar Conference On Signals, Systems and Computers. 2: 1031-1034.  0.779
1999 Parhi KK. Low-energy CSMT carry generators and binary adders Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 7: 450-462. DOI: 10.1109/92.805752  0.396
1999 Denk TC, Parhi KK. Two-dimensional retiming Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 7: 198-211. DOI: 10.1109/92.766747  0.301
1999 Shalash AF, Parhi KK. Multidimensional carrierless AM/PM systems for digital subscriber loops Ieee Transactions On Communications. 47: 1655-1667. DOI: 10.1109/26.803500  0.423
1999 Srinivas HR, Parhi KK. Radix 2 shared division/square root algorithm and its VLSI architecture Journal of Vlsi Signal Processing Systems For Signal, Image, and Video Technology. 21: 37-60. DOI: 10.1023/A:1008075621962  0.308
1998 Denk TC, Parhi KK. Synthesis of folded pipelined architectures for multirate DSP algorithms Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 6: 595-607. DOI: 10.1109/92.736133  0.448
1998 Ito K, Lucke L, Parhi K. ILP-based cost-optimal DSP synthesis with module selection and data format conversion Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 6: 582-594. DOI: 10.1109/92.736132  0.406
1998 Jain S, Song L, Parhi K. Efficient semisystolic architectures for finite-field arithmetic Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 6: 101-113. DOI: 10.1109/92.661252  0.447
1998 Chang Y, Satyanarayana JH, Parhi KK. Systematic design of high-speed and low-power digit-serial multipliers Ieee Transactions On Circuits and Systems Ii: Analog and Digital Signal Processing. 45: 1585-1596. DOI: 10.1109/82.746672  0.424
1998 Denk TC, Parhi KK. Exhaustive scheduling and retiming of digital signal processing systems Ieee Transactions On Circuits and Systems Ii: Analog and Digital Signal Processing. 45: 821-838. DOI: 10.1109/82.700929  0.376
1998 Majumdar M, Parhi K. Design of data format converters using two-dimensional register allocation Ieee Transactions On Circuits and Systems Ii: Analog and Digital Signal Processing. 45: 504-508. DOI: 10.1109/82.663807  0.36
1998 Montalvo L, Parhi K, Guyot A. New Svoboda-Tung division Ieee Transactions On Computers. 47: 1014-1020. DOI: 10.1109/12.713319  0.371
1997 Li Y, Parhi KK. STAR recursive least square lattice adaptive filters Ieee Transactions On Circuits and Systems Ii: Analog and Digital Signal Processing. 44: 1040-1054. DOI: 10.1109/82.644588  0.346
1997 Satyanarayana JH, Parhi KK. A theoretical approach to estimation of bounds on power consumption in digital multipliers Ieee Transactions On Circuits and Systems Ii: Analog and Digital Signal Processing. 44: 473-481. DOI: 10.1109/82.592578  0.359
1997 Denk TC, Parhi KK. VLSI architectures for lattice structure based orthonormal discrete wavelet transforms Ieee Transactions On Circuits and Systems Ii: Analog and Digital Signal Processing. 44: 129-132. DOI: 10.1109/82.554448  0.419
1997 Raghunath KJ, Parhi KK. Finite-precision error analysis of QRD-RLS and STAR-RLS adaptive filters Ieee Transactions On Signal Processing. 45: 1193-1209. DOI: 10.1109/78.575694  0.383
1997 Fu B, Parhi KK. Generalized multiplication-free arithmetic codes Ieee Transactions On Communications. 45: 497-501. DOI: 10.1109/26.592545  0.39
1997 Srinivas H, Parhi K, Montalvo L. Radix 2 division with over-redundant quotient selection Ieee Transactions On Computers. 46: 85-92. DOI: 10.1109/12.559806  0.439
1996 Raghunath KJ, Parhi KK. Pipelined RLS adaptive filtering using scaled tangent rotations (STAR) Ieee Transactions On Signal Processing. 44: 2591-2604. DOI: 10.1109/78.539042  0.403
1996 Song L, Parhi KK. Efficient finite field serial/parallel multiplication International Conference On Application-Specific Systems, Architectures and Processors, Proceedings. 72-82.  0.332
1995 Chung J, Kim H, Parhi KK. Pipelined lattice WDF design for wideband filters Ieee Transactions On Circuits and Systems Ii: Analog and Digital Signal Processing. 42: 616-618. DOI: 10.1109/82.466640  0.365
1995 Chung JG, Parhi KK. Scaled Normalized Lattice Digital Filter Structures Ieee Transactions On Circuits and Systems Ii: Analog and Digital Signal Processing. 42: 278-282. DOI: 10.1109/82.378042  0.319
1995 Shanbhag NR, Parhi KK. Pipelined Adaptive DFE Architectures Using Relaxed Look-Ahead Ieee Transactions On Signal Processing. 43: 1368-1385. DOI: 10.1109/78.388851  0.667
1995 Wang CY, Parhi KK. High-Level DSP Synthesis Using Concurrent Transformations, Scheduling, and Allocation Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 14: 274-295. DOI: 10.1109/43.365120  0.427
1995 Srinivas H, Parhi K. A fast radix-4 division algorithm and its architecture Ieee Transactions On Computers. 44: 826-831. DOI: 10.1109/12.391179  0.426
1995 Parhi KK. High-level algorithm and architecture transformations for DSP synthesis Journal of Vlsi Signal Processing. 9: 121-143. DOI: 10.1007/BF02406474  0.313
1994 Srinivas H, Vinnakota B, Parhi K. A C-testable carry-free divider Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 2: 472-488. DOI: 10.1109/92.335015  0.316
1994 Parhi KK. Calculation of Minimum Number of Registers in Arbitrary life time Chart Ieee Transactions On Circuits and Systems Ii: Analog and Digital Signal Processing. 41: 434-436. DOI: 10.1109/82.300209  0.308
1994 Shanbhag NR, Parhi KK. Corrections to “Finite-Precision Analysis of the Pipelined ADPCM Coder”<sup>1</sup> Ieee Transactions On Circuits and Systems Ii: Analog and Digital Signal Processing. 41: 493. DOI: 10.1109/82.298386  0.54
1994 Shanbhag NR, Parhi KK. Finite-Precision Analysis of the Pipelined ADPCM Coder Ieee Transactions On Circuits and Systems Ii: Analog and Digital Signal Processing. 41: 364-368. DOI: 10.1109/82.287009  0.604
1994 Lucke LE, Parhi KK. Parallel Processing Architectures for Rank Order and Stack Filters Ieee Transactions On Signal Processing. 42: 1178-1189. DOI: 10.1109/78.295200  0.405
1994 Chung JG, Parhi KK. Pipelining of Lattice IIR Digital Filters Ieee Transactions On Signal Processing. 42: 751-761. DOI: 10.1109/78.285640  0.362
1994 Parhi K, Wu F, Genesan K. Sequential and parallel neural network vector quantizers Ieee Transactions On Computers. 43: 104-109. DOI: 10.1109/12.250614  0.305
1994 Adams GB, Coyle EJ, Lin L, Lucke LE, Parhi KK. Input compression and efficient VLSI architectures for rank order and stack filters Signal Processing. 38: 441-453. DOI: 10.1016/0165-1684(94)90159-7  0.378
1993 Parhi KK, Nishitani T. VLSI Architectures for Discrete Wavelet Transforms Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 1: 191-202. DOI: 10.1109/92.238416  0.481
1993 Shanbhag NR, Parhi KK. Relaxed Look-Ahead Pipelined LMS Adaptive Filters and Their Application to ADPCM Coder Ieee Transactions On Circuits and Systems Ii: Analog and Digital Signal Processing. 40: 753-766. DOI: 10.1109/82.260240  0.667
1993 Shanbhag NR, Parhi KK. A Pipelined Adaptive Differential Vector Quantizer for Low-Power Speech Coding Applications Ieee Transactions On Circuits and Systems Ii: Analog and Digital Signal Processing. 40: 347-349. DOI: 10.1109/82.227377  0.671
1993 Raghunath KJ, Parhi KK. Parallel Adaptive Decision Feedback Equalizers Ieee Transactions On Signal Processing. 41: 1956-1961. DOI: 10.1109/78.215315  0.423
1993 Shanbhag NR, Parhi KK. A Pipelined Adaptive Lattice Filter Architecture Ieee Transactions On Signal Processing. 41: 1925-1939. DOI: 10.1109/78.215309  0.658
1993 Lucke LE, Parhi KK. Data-Flow Transformations for Critical Path Time Reduction in High-Level DSP Synthesis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 12: 1063-1068. DOI: 10.1109/43.238043  0.341
1992 Parhi K. Systematic synthesis of DSP data format converters using life-time analysis and forward-backward register allocation Ieee Transactions On Circuits and Systems Ii: Analog and Digital Signal Processing. 39: 423-440. DOI: 10.1109/82.160168  0.349
1992 Parhi KK. High-Speed VLSI Architectures for Huffman and Viterbi Decoders Ieee Transactions On Circuits and Systems Ii: Analog and Digital Signal Processing. 39: 385-391. DOI: 10.1109/82.145297  0.484
1992 Parhi KK. Video Data Format Converters Using Minimum Number of Registers Ieee Transactions On Circuits and Systems For Video Technology. 2: 255-267. DOI: 10.1109/76.143424  0.3
1992 Srinivas HR, Parhi KK. A Fast VLSI Adder Architecture Ieee Journal of Solid-State Circuits. 27: 761-767. DOI: 10.1109/4.133165  0.471
1992 Hatamian M, Parhi KK. An 85-MHz Fourth-Order Programmable IIR Digital Filter Chip Ieee Journal of Solid-State Circuits. 27: 175-183. DOI: 10.1109/4.127340  0.388
1992 Parhi KK, Wang CY, Brown AP. Synthesis of Control Circuits in Folded Pipelined DSP Architectures Ieee Journal of Solid-State Circuits. 27: 29-43. DOI: 10.1109/4.109555  0.39
1992 Srinivas HR, Parhi KK. High-speed VLSI arithmetic processor architectures using hybrid number representation Journal of Vlsi Signal Processing. 4: 177-198. DOI: 10.1007/BF00925121  0.341
1991 Parhi KK. Finite Word Effects in Pipelined Recursive Filters Ieee Transactions On Signal Processing. 39: 1450-1454. DOI: 10.1109/78.136557  0.317
1991 Parhi KK. Pipelining in Dynamic Programming Architectures Ieee Transactions On Signal Processing. 39: 1442-1450. DOI: 10.1109/78.136556  0.437
1991 Parhi K. A systematic approach for design of digit-serial signal processing architectures Ieee Transactions On Circuits and Systems. 38: 358-375. DOI: 10.1109/31.75394  0.464
1991 Parhi KK. Pipelining in Algorithms with Quantizer Loops Ieee Transactions On Circuits and Systems. 38: 745-754. DOI: 10.1109/31.135746  0.443
1991 Parhi KK, Messerschmitt DG. Static Rate-Optimal Scheduling of Iterative Data-Flow Programs via Optimum Unfolding Ieee Transactions On Computers. 40: 178-195. DOI: 10.1109/12.73588  0.563
1989 Parhi KK, Messerschmitt DG. Concurrent Architectures for Two-Dimensional Recursive Digital Filtering Ieee Transactions On Circuits and Systems. 36: 813-829. DOI: 10.1109/31.90397  0.664
1989 Parhi KK, Messerschmitt DG. Pipeline Interleaving and Parallelism in Recursive Digital Filters—Part II: Pipelined Incremental Block Filtering Ieee Transactions On Acoustics, Speech, and Signal Processing. 37: 1118-1134. DOI: 10.1109/29.32287  0.642
1989 Parhi KK, Messerschmitt DG. Pipeline Interleaving and Parallelism in Recursive Digital Filters—Part I: Pipelining Using Scattered Look-Ahead and Decomposition Ieee Transactions On Acoustics, Speech, and Signal Processing. 37: 1099-1117. DOI: 10.1109/29.32286  0.664
1987 Parhi KK, Messerschmitt DG. Concurrent Cellular VLSI Adaptive Filter Architectures Ieee Transactions On Circuits and Systems. 34: 1141-1151. DOI: 10.1109/Tcs.1987.1086048  0.65
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