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Premkishore Shivakumar, Ph.D. - Publications

Affiliations: 
2007 Computer Sciences University of Texas at Austin, Austin, Texas, U.S.A. 
Area:
Computer Science
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7 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2007 Gratz P, Kim C, Sankaralingam K, Hanson H, Shivakumar P, Keckler SW, Burger D. On-chip interconnection networks of the TRIPS chip Ieee Micro. 27: 41-50. DOI: 10.1109/Mm.2007.90  0.561
2006 Sankaralingam K, Nagarajan R, McDonald R, Desikan R, Drolia S, Govindan MS, Gratz P, Gulati D, Hanson H, Kim C, Liu H, Ranganathan N, Sethumadhavan S, Sharif S, Shivakumar P, et al. Distributed microarchitectural protocols in the TRIPS prototype processor Proceedings of the Annual International Symposium On Microarchitecture, Micro. 480-491. DOI: 10.1109/MICRO.2006.19  0.654
2003 Shivakumar P, Keckler SW, Moore CR, Burger D. Exploiting microarchitectural redundancy for defect tolerance Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 481-488. DOI: 10.1109/ICCD.2012.6378613  0.608
2003 Shivakumar P, Keckler SW, Moore CR, Burger D. Exploiting microarchitectural redundancy for defect tolerance Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 481-488.  0.369
2003 Keckler SW, Burger D, Moore CR, Nagarajan R, Sankaralingam K, Agarwal V, Hrishikesh MS, Ranganathan N, Shivakumar P. A wire-delay scalable microprocessor architecture for high performance systems Digest of Technical Papers - Ieee International Solid-State Circuits Conference.  0.659
2002 Shivakumar P, Kistler M, Keckler SW, Burger D, Alvisi L. Modeling the effect of technology trends on the soft error rate of combinational logic Proceedings of the 2002 International Conference On Dependable Systems and Networks. 389-398. DOI: 10.1109/DSN.2002.1028924  0.589
2002 Hrishikesh MS, Jouppi NP, Farkas KI, Burger D, Keckler SW, Shivakumar P. The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays Conference Proceedings - Annual International Symposium On Computer Architecture, Isca. 14-24.  0.591
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