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Zhongfeng Wang, Ph.D. - Publications

Affiliations: 
2000 University of Minnesota, Twin Cities, Minneapolis, MN 
Area:
Electronics and Electrical Engineering
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79 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2023 Shi Y, Wang M, Cao T, Lin J, Wang Z. TECO: A Unified Feature Map Compression Framework Based on Transform and Entropy. Ieee Transactions On Neural Networks and Learning Systems. PMID 37703155 DOI: 10.1109/TNNLS.2023.3309667  0.33
2023 Xie X, Zhu M, Lu S, Wang Z. Efficient Layer-Wise : Sparse CNN Accelerator with Flexible SPEC: Sparse Processing Element Clusters. Micromachines. 14. PMID 36984936 DOI: 10.3390/mi14030528  0.312
2021 Mao W, Yang P, Wang Z. FTA-GAN: A Computation-Efficient Accelerator for GANs With Fast Transformation Algorithm. Ieee Transactions On Neural Networks and Learning Systems. PMID 34534090 DOI: 10.1109/TNNLS.2021.3110728  0.326
2020 Mao W, Lin J, Wang Z. F-DNA: Fast Convolution Architecture for Deconvolutional Network Acceleration Ieee Transactions On Very Large Scale Integration Systems. 28: 1867-1880. DOI: 10.1109/Tvlsi.2020.3000519  0.423
2020 Wang Y, Luo Y, Wang Z, Shen Q, Pan H. GH CORDIC-Based Architecture for Computing $N$ th Root of Single-Precision Floating-Point Number Ieee Transactions On Very Large Scale Integration Systems. 28: 864-875. DOI: 10.1109/Tvlsi.2019.2959847  0.41
2020 Qin Z, Qiu Y, Sun H, Lu Z, Wang Z, Shen Q, Pan H. A Novel Approximation Methodology and Its Efficient VLSI Implementation for the Sigmoid Function Ieee Transactions On Circuits and Systems Ii-Express Briefs. 1-1. DOI: 10.1109/Tcsii.2020.2999458  0.339
2020 Chen Y, Cui H, Lin J, Wang Z. Fine-Grained Bit-Flipping Decoding for LDPC Codes Ieee Transactions On Circuits and Systems Ii-Express Briefs. 67: 896-900. DOI: 10.1109/Tcsii.2020.2980846  0.499
2020 Song S, Cui H, Tian J, Lin J, Wang Z. A Novel Iterative Reliability-Based Majority-Logic Decoder for NB-LDPC Codes Ieee Transactions On Circuits and Systems Ii-Express Briefs. 67: 1399-1403. DOI: 10.1109/Tcsii.2019.2938562  0.541
2020 Tian J, Song S, Lin J, Wang Z. Optimized Trellis-Based Min-Max Decoder for NB-LDPC Codes Ieee Transactions On Circuits and Systems Ii-Express Briefs. 67: 57-61. DOI: 10.1109/Tcsii.2019.2900088  0.549
2020 Li W, Lin J, Wang Z. Multi-Layer Generalized Integrated Interleaved Codes Ieee Communications Letters. 24: 1880-1884. DOI: 10.1109/Lcomm.2020.2997693  0.477
2019 Luo Y, Wang Y, Ha Y, Wang Z, Chen S, Pan H. Corrections to “Generalized Hyperbolic CORDIC and Its Logarithmic and Exponential Computation With Arbitrary Fixed Base” Ieee Transactions On Very Large Scale Integration Systems. 27: 2222-2222. DOI: 10.1109/Tvlsi.2019.2932174  0.312
2019 Luo Y, Wang Y, Ha Y, Wang Z, Chen S, Pan H. Generalized Hyperbolic CORDIC and Its Logarithmic and Exponential Computation With Arbitrary Fixed Base Ieee Transactions On Very Large Scale Integration Systems. 27: 2156-2169. DOI: 10.1109/Tvlsi.2019.2919557  0.413
2019 Zhu C, Liang R, Lin J, Wang Z, Li L. Analysis and Design of a Large Dither Injection Circuit for Improving Linearity in Pipelined ADCs Ieee Transactions On Very Large Scale Integration Systems. 27: 2008-2020. DOI: 10.1109/Tvlsi.2019.2912421  0.374
2019 Zhu C, Lin J, Wang Z. Background Calibration of Comparator Offsets in SHA-Less Pipelined ADCs Ieee Transactions On Circuits and Systems Ii-Express Briefs. 66: 357-361. DOI: 10.1109/Tcsii.2018.2854571  0.391
2019 Zhu C, Lin J, Wang Z. A New Clock Phase Calibration Method in High-Speed and High-Resolution DACs Ieee Transactions On Circuits and Systems Ii-Express Briefs. 66: 332-336. DOI: 10.1109/Tcsii.2018.2850922  0.383
2019 Cui H, Lin J, Wang Z. An Efficient Post-Processor for Lowering the Error Floor of LDPC Codes Ieee Transactions On Circuits and Systems Ii-Express Briefs. 66: 397-401. DOI: 10.1109/Tcsii.2018.2849504  0.565
2019 Zhou Y, Chen Z, Lin J, Wang Z. A High-Speed Successive-Cancellation Decoder for Polar Codes Using Approximate Computing Ieee Transactions On Circuits and Systems Ii-Express Briefs. 66: 227-231. DOI: 10.1109/Tcsii.2018.2847441  0.561
2019 Li W, Lin J, Wang Z. A 124-Gb/s Decoder for Generalized Integrated Interleaved Codes Ieee Transactions On Circuits and Systems I-Regular Papers. 66: 3174-3187. DOI: 10.1109/Tcsi.2019.2911730  0.588
2019 Cui H, Lin J, Wang Z. An Improved Gradient Descent Bit-Flipping Decoder for LDPC Codes Ieee Transactions On Circuits and Systems I-Regular Papers. 66: 3188-3200. DOI: 10.1109/Tcsi.2019.2909653  0.507
2019 Wang Y, Lin J, Wang Z. FPAP: A Folded Architecture for Energy-Quality Scalable Convolutional Neural Networks Ieee Transactions On Circuits and Systems I-Regular Papers. 66: 288-301. DOI: 10.1109/Tcsi.2018.2856624  0.427
2019 Zhou Y, Lin J, Wang Z. Improved Fast-SSC-Flip Decoding of Polar Codes Ieee Communications Letters. 23: 950-953. DOI: 10.1109/Lcomm.2019.2910059  0.518
2019 Li W, Tian J, Lin J, Wang Z. Modified GII-BCH Codes for Low-Complexity and Low-Latency Encoders Ieee Communications Letters. 23: 785-788. DOI: 10.1109/Lcomm.2019.2908867  0.529
2019 Wang M, Wang Z, Lu J, Lin J, Wang Z. E-LSTM: An Efficient Hardware Architecture for Long Short-Term Memory Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 9: 280-291. DOI: 10.1109/Jetcas.2019.2911739  0.436
2019 Lu S, Lu J, Lin J, Wang Z. A Hardware-Oriented and Memory-Efficient Method for CTC Decoding Ieee Access. 7: 120681-120694. DOI: 10.1109/Access.2019.2937680  0.444
2019 Tian J, Song S, Lin J, Wang Z. Efficient T-EMS Based Decoding Algorithms for High-Order LDPC Codes Ieee Access. 7: 50980-50992. DOI: 10.1109/Access.2019.2910240  0.556
2019 Liu X, Zi L, Yang D, Wang Z. Improved Decoding Algorithms of LDPC Codes Based on Reliability Metrics of Variable Nodes Ieee Access. 7: 35769-35778. DOI: 10.1109/Access.2019.2904173  0.44
2018 Zhang C, Ge L, Zhang X, Wei W, Zhao J, Zhang Z, Wang Z, You X. A Uniform Molecular Low-Density Parity-Check Decoder. Acs Synthetic Biology. PMID 30513194 DOI: 10.1021/acssynbio.8b00304  0.464
2018 Wang Y, Lin J, Wang Z. An Energy-Efficient Architecture for Binary Weight Convolutional Neural Networks Ieee Transactions On Very Large Scale Integration Systems. 26: 280-293. DOI: 10.1109/Tvlsi.2017.2767624  0.478
2018 Zeng J, Lin J, Wang Z. An Improved Gauss-Seidel Algorithm and Its Efficient Architecture for Massive MIMO Systems Ieee Transactions On Circuits and Systems Ii-Express Briefs. 65: 1194-1198. DOI: 10.1109/Tcsii.2018.2801867  0.451
2018 Tian J, Lin J, Wang Z. A 21.66 Gbps Nonbinary LDPC Decoder for High-Speed Communications Ieee Transactions On Circuits and Systems Ii-Express Briefs. 65: 226-230. DOI: 10.1109/Tcsii.2017.2706273  0.609
2018 Luo Y, Wang Y, Sun H, Zha Y, Wang Z, Pan H. CORDIC-Based Architecture for Computing Nth Root and Its Implementation Ieee Transactions On Circuits and Systems I-Regular Papers. 65: 4183-4195. DOI: 10.1109/Tcsi.2018.2835822  0.445
2018 Wang J, Lin J, Wang Z. Efficient Hardware Architectures for Deep Convolutional Neural Network Ieee Transactions On Circuits and Systems I-Regular Papers. 65: 1941-1953. DOI: 10.1109/Tcsi.2017.2767204  0.468
2018 Liu X, Xiong F, Wang Z, Liang S. Design of Binary LDPC Codes With Parallel Vector Message Passing Ieee Transactions On Communications. 66: 1363-1375. DOI: 10.1109/Tcomm.2017.2783624  0.518
2018 Zeng J, Lin J, Wang Z. Low Complexity Message Passing Detection Algorithm for Large-Scale MIMO Systems Ieee Wireless Communications Letters. 7: 708-711. DOI: 10.1109/Lwc.2018.2813386  0.449
2018 Wang Z, Lin J, Wang Z. Hardware-Oriented Compression of Long Short-Term Memory for Efficient Inference Ieee Signal Processing Letters. 25: 984-988. DOI: 10.1109/Lsp.2018.2834872  0.405
2018 Sha J, Liu J, Lin J, Wang Z. A Stage-Combined Belief Propagation Decoder for Polar Codes Journal of Signal Processing Systems. 90: 687-694. DOI: 10.1007/S11265-016-1181-Y  0.561
2017 Wang Z, Lin J, Wang Z. Accelerating Recurrent Neural Networks: A Memory-Efficient Approach Ieee Transactions On Very Large Scale Integration Systems. 25: 2763-2775. DOI: 10.1109/Tvlsi.2017.2717950  0.426
2017 Hu G, Sha J, Wang Z. High-Speed Parallel LFSR Architectures Based on Improved State-Space Transformations Ieee Transactions On Very Large Scale Integration Systems. 25: 1159-1163. DOI: 10.1109/Tvlsi.2016.2608921  0.402
2017 Lin J, Yan Z, Wang Z. Efficient Soft Cancelation Decoder Architectures for Polar Codes Ieee Transactions On Very Large Scale Integration Systems. 25: 87-99. DOI: 10.1109/Tvlsi.2016.2577883  0.463
2017 Xie Y, Liao S, Yuan B, Wang Y, Wang Z. Fully-Parallel Area-Efficient Deep Neural Network Design Using Stochastic Computing Ieee Transactions On Circuits and Systems Ii-Express Briefs. 64: 1382-1386. DOI: 10.1109/Tcsii.2017.2746749  0.555
2017 Zhou J, Zavareh AT, Gupta R, Liu L, Wang Z, Sadler BM, Silva-Martinez J, Hoyos S. Compressed Level Crossing Sampling for Ultra-Low Power IoT Devices Ieee Transactions On Circuits and Systems I: Regular Papers. 64: 2495-2507. DOI: 10.1109/Tcsi.2017.2707481  0.428
2017 Zhang C, Huang Y, Sheikh F, Wang Z. Advanced Baseband Processing Algorithms, Circuits, and Implementations for 5G Communication Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 7: 477-490. DOI: 10.1109/Jetcas.2017.2743107  0.355
2016 Yuan B, Wang Y, Wang Z. Area-Efficient Scaling-Free DFT/FFT Design Using Stochastic Computing Ieee Transactions On Circuits and Systems Ii-Express Briefs. 63: 1131-1135. DOI: 10.1109/Tcsii.2016.2603465  0.505
2014 Zhang C, Wang Z, You X. Efficient Decoder Architecture for Single Block-Row Quasi-Cyclic LDPC Codes Ieee Transactions On Circuits and Systems Ii-Express Briefs. 61: 793-797. DOI: 10.1109/Tcsii.2014.2345290  0.53
2013 Cideciyan RD, Gustlin M, Li MP, Wang J, Wang Z. Next generation backplane and copper cable challenges Ieee Communications Magazine. 51: 130-136. DOI: 10.1109/Mcom.2013.6685768  0.344
2012 Li L, Yuan B, Wang Z, Sha J, Pan H, Zheng W. Unified Architecture for Reed-Solomon Decoder Combined With Burst-Error Correction Ieee Transactions On Very Large Scale Integration Systems. 20: 1346-1350. DOI: 10.1109/Tvlsi.2011.2154369  0.586
2012 He J, Liu H, Wang Z, Huang X, Zhang K. High-Speed Low-Power Viterbi Decoder Design for TCM Decoders Ieee Transactions On Very Large Scale Integration Systems. 20: 755-759. DOI: 10.1109/Tvlsi.2011.2111392  0.519
2012 Zhang X, Wang Z. A Low-Complexity Three-Error-Correcting BCH Decoder for Optical Transport Network Ieee Transactions On Circuits and Systems Ii-Express Briefs. 59: 663-667. DOI: 10.1109/Tcsii.2012.2208678  0.634
2012 He K, Sha J, Wang Z. Nonbinary LDPC Code Decoder Architecture With Efficient Check Node Processing Ieee Transactions On Circuits and Systems Ii-Express Briefs. 59: 381-385. DOI: 10.1109/Tcsii.2012.2195058  0.566
2012 Wang Z. Super-FEC Codes for 40/100 Gbps Networking Ieee Communications Letters. 16: 2056-2059. DOI: 10.1109/Lcomm.2012.112012.122083  0.519
2011 Zhao P, McNeely J, Kuang W, Wang N, Wang Z. Design of Sequential Elements for Low Power Clocking System Ieee Transactions On Very Large Scale Integration Systems. 19: 914-918. DOI: 10.1109/Tvlsi.2009.2038705  0.34
2011 Zhang K, Huang X, Wang Z. A High-Throughput LDPC Decoder Architecture With Rate Compatibility Ieee Transactions On Circuits and Systems. 58: 839-847. DOI: 10.1109/Tcsi.2010.2089551  0.528
2011 Wang Z, Cui Z, Sha J. Vlsi design for low-density parity-check code decoding Ieee Circuits and Systems Magazine. 11: 52-69. DOI: 10.1109/Mcas.2010.939785  0.54
2011 Cui Z, Wang Z, Zhang X. Reduced-complexity column-layered decoding and implementation for LDPC codes Iet Communications. 5: 2177-2186. DOI: 10.1049/Iet-Com.2010.1002  0.679
2010 He J, Wang Z, Liu H. An Efficient 4-D 8PSK TCM Decoder Architecture Ieee Transactions On Very Large Scale Integration Systems. 18: 808-817. DOI: 10.1109/Tvlsi.2009.2015325  0.455
2010 Lin J, Sha J, Wang Z, Li L. An Efficient VLSI Architecture for Nonbinary LDPC Decoders Ieee Transactions On Circuits and Systems Ii-Express Briefs. 57: 51-55. DOI: 10.1109/Tcsii.2009.2036542  0.59
2010 Lin J, Sha J, Wang Z, Li L. Efficient Decoder Design for Nonbinary Quasicyclic LDPC Codes Ieee Transactions On Circuits and Systems I-Regular Papers. 57: 1071-1082. DOI: 10.1109/Tcsi.2010.2046196  0.551
2010 Zhang C, Wang Z, Sha J, Li L, Lin J. Flexible LDPC Decoder Design for Multigigabit-per-Second Applications Ieee Transactions On Circuits and Systems I-Regular Papers. 57: 116-124. DOI: 10.1109/Tcsi.2009.2018915  0.593
2010 Zhang K, Huang X, Wang Z. A dual-rate LDPC decoder for china multimedia mobile broadcasting systems Ieee Transactions On Consumer Electronics. 56: 399-407. DOI: 10.1109/Tce.2010.5505946  0.52
2009 Zhu J, Zhang X, Wang Z. Backward Interpolation Architecture for Algebraic Soft-Decision Reed–Solomon Decoding Ieee Transactions On Very Large Scale Integration Systems. 17: 1602-1615. DOI: 10.1109/Tvlsi.2008.2005575  0.702
2009 Cui Z, Wang Z, Liu Y. High-Throughput Layered LDPC Decoding Architecture Ieee Transactions On Very Large Scale Integration Systems. 17: 582-587. DOI: 10.1109/Tvlsi.2008.2005308  0.533
2009 Sha J, Wang Z, Gao M, Li L. Multi-Gb/s LDPC Code Design and Implementation Ieee Transactions On Very Large Scale Integration Systems. 17: 262-268. DOI: 10.1109/Tvlsi.2008.2002487  0.569
2009 Sha J, Lin J, Wang Z, Li L, Gao M. Decoder Design for RS-Based LDPC Codes Ieee Transactions On Circuits and Systems Ii-Express Briefs. 56: 724-728. DOI: 10.1109/Tcsii.2009.2027945  0.55
2009 Yuan B, Wang Z, Li L, Gao M, Sha J, Zhang C. Area-efficient reed-solomon decoder design for optical communications Ieee Transactions On Circuits and Systems Ii-Express Briefs. 56: 469-473. DOI: 10.1109/Tcsii.2009.2020928  0.598
2009 Lin J, Wang Z, Li L, Sha J, Gao M. Efficient Shuffle Network Architecture and Application for WiMAX LDPC Decoders Ieee Transactions On Circuits and Systems Ii-Express Briefs. 56: 215-219. DOI: 10.1109/Tcsii.2009.2015353  0.383
2009 Wu Z, Sha J, Wang Z, Li L, Gao M. An improved scaled DCT architecture Ieee Transactions On Consumer Electronics. 55: 685-689. DOI: 10.1109/Tce.2009.5174440  0.437
2009 Sha J, Lin J, Wang Z, Li L, Gao M. LDPC decoder design for high rate wireless personal area networks Ieee Transactions On Consumer Electronics. 55: 455-460. DOI: 10.1109/Tce.2009.5174407  0.542
2009 Zhang K, Huang X, Wang Z. High-throughput layered decoder implementation for quasi-cyclic LDPC codes Ieee Journal On Selected Areas in Communications. 27: 985-994. DOI: 10.1109/Jsac.2009.090816  0.524
2008 Cui Z, Wang Z. Improved low-complexity low-density parity-check decoding Iet Communications. 2: 1061-1068. DOI: 10.1049/Iet-Com:20070570  0.547
2007 Ma J, Vardy A, Wang Z. Low-Latency Factorization Architecture for Algebraic Soft-Decision Decoding of Reed–Solomon Codes Ieee Transactions On Very Large Scale Integration Systems. 15: 1225-1238. DOI: 10.1109/Tvlsi.2007.904173  0.515
2007 Wang Z. High-Speed Recursion Architectures for MAP-Based Turbo Decoders Ieee Transactions On Very Large Scale Integration Systems. 15: 470-474. DOI: 10.1109/Tvlsi.2007.893668  0.492
2007 Wang Z, Cui Z. Low-Complexity High-Speed Decoder Design for Quasi-Cyclic LDPC Codes Ieee Transactions On Very Large Scale Integration Systems. 15: 104-114. DOI: 10.1109/Tvlsi.2007.891098  0.604
2007 Wang Z, Cui Z. A Memory Efficient Partially Parallel Decoder Architecture for Quasi-Cyclic LDPC Codes Ieee Transactions On Very Large Scale Integration Systems. 15: 483-488. DOI: 10.1109/Ted.2007.895247  0.561
2007 Wang Z, Li Q. Very Low-Complexity Hardware Interleaver for Turbo Decoding Ieee Transactions On Circuits and Systems Ii-Express Briefs. 54: 636-640. DOI: 10.1109/Tcsii.2007.895313  0.527
2006 Wang Z, Jun M. High-speed interpolation architecture for soft-decision decoding of reed-solomon codes Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 14: 937-950. DOI: 10.1109/Tvlsi.2006.884046  0.526
2004 Chi Z, Wang Z, Parhi K. On the Better Protection of Short-Frame Turbo Codes Ieee Transactions On Communications. 52: 1435-1439. DOI: 10.1109/Tcomm.2004.833144  0.707
2003 Wang Z, Parhi KK. High performance, high throughput turbo/SOVA decoder design Ieee Transactions On Communications. 51: 570-579. DOI: 10.1109/Tcomm.2003.810832  0.678
2002 Wang Z, Chi Z, Parhi KK. Area-efficient high-speed decoding schemes for turbo decoders Ieee Transactions On Very Large Scale Integration Systems. 10: 902-912. DOI: 10.1109/Tvlsi.2002.808451  0.717
2002 Wang Z, Parhi KK. On-line extraction of soft decoding information and applications in VLSI turbo decoding Ieee Transactions On Circuits and Systems Ii: Analog and Digital Signal Processing. 49: 760-769. DOI: 10.1109/Tcsii.2002.807759  0.606
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