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Yajun Ran, Ph.D. - Publications

Affiliations: 
2005 University of California, Santa Barbara, Santa Barbara, CA, United States 
Area:
Electronics and Electrical Engineering, Computer Science
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9 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2006 Ran Y, Marek-Sadowska M. Via-configurable routing architectures and fast design mappability estimation for regular fabrics Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 14: 998-1009. DOI: 10.1109/Tvlsi.2006.884051  0.582
2006 Ran Y, Marek-Sadowska M. Designing via-configurable logic blocks for regular fabric Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 14: 1-14. DOI: 10.1109/Tvlsi.2005.863196  0.575
2005 Ran Y, Kondratyev A, Tseng KH, Watanabe Y, Marek-Sadowska M. Eliminating false positives in crosstalk noise analysis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 24: 1406-1419. DOI: 10.1109/Tcad.2005.850829  0.523
2005 Wang K, Ran Y, Jiang H, Marek-Sadowska M. General skew constrained clock network sizing based on sequential linear programming Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 24: 773-781. DOI: 10.1109/Tcad.2005.846362  0.567
2004 Ran Y, Marek-Sadowska M. An integrated design flow for a via-configurable gate array Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 582-589. DOI: 10.1109/ICCAD.2004.1382644  0.538
2004 Ran Y, Marek-Sadowska M. On designing via-configurable cell blocks for regular fabrics Proceedings - Design Automation Conference. 198-203. DOI: 10.1109/DAC.2004.240257  0.546
2004 Ran Y, Marek-Sadowska M. Designing a via-configurable regular fabric Proceedings of the Custom Integrated Circuits Conference. 423-426.  0.57
2004 Ran Y, Marek-Sadowska M. The magic of a via-configurable regular fabric Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 338-343.  0.557
2003 Ran Y, Marek-Sadowska M. Crosstalk noise in FPGAs Proceedings - Design Automation Conference. 944-949.  0.498
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