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Linda Milor - Publications

Affiliations: 
Georgia Institute of Technology, Atlanta, GA 
Area:
Electronics and Electrical Engineering, Computer Engineering, Statistics
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39 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Wu Y, Yang K, Hsu S, Milor L. Optimal Accelerated Test Framework for Time-Dependent Dielectric Breakdown Lifetime Parameter Estimation Ieee Transactions On Very Large Scale Integration Systems. 1-14. DOI: 10.1109/Tvlsi.2020.3017950  0.334
2020 Zhang R, Liu T, Yang K, Chen C, Milor L. SRAM Stability Analysis and Performance–Reliability Tradeoff for Different Cache Configurations Ieee Transactions On Very Large Scale Integration Systems. 28: 620-633. DOI: 10.1109/Tvlsi.2019.2956923  0.439
2019 Kim D, Hsu S, Milor L. Optimization of Experimental Designs for System- Level Accelerated Life Test in a Memory System Degraded by Time-Dependent Dielectric Breakdown Ieee Transactions On Very Large Scale Integration Systems. 27: 1640-1651. DOI: 10.1109/Tvlsi.2019.2909086  0.404
2019 Zhang R, Liu Z, Yang K, Liu T, Cai W, Milor L. Impact of front-end wearout mechanisms on FinFET SRAM soft error rate Microelectronics Reliability. 113487. DOI: 10.1016/J.Microrel.2019.113487  0.35
2019 Zhang R, Liu Z, Yang K, Liu T, Cai W, Milor L. A library based on deep neural networks for modeling the degradation of FinFET SRAM performance metrics due to aging Microelectronics Reliability. 113486. DOI: 10.1016/J.Microrel.2019.113486  0.425
2019 Zhang R, Yang KX, Liu TZ, Milor L. Modeling of FinFET SRAM array reliability degradation due to electromigration Microelectronics Reliability. 113485. DOI: 10.1016/J.Microrel.2019.113485  0.387
2018 Yang K, Liu T, Zhang R, Milor L. A Comprehensive Time-Dependent Dielectric Breakdown Lifetime Simulator for Both Traditional CMOS and FinFET Technology Ieee Transactions On Very Large Scale Integration Systems. 26: 2470-2482. DOI: 10.1109/Tvlsi.2018.2861769  0.454
2018 Liu T, Chen C, Milor L. Comprehensive Reliability-Aware Statistical Timing Analysis Using a Unified Gate-Delay Model for Microprocessors Ieee Transactions On Emerging Topics in Computing. 6: 219-232. DOI: 10.1109/Tetc.2016.2588724  0.428
2017 Cha S, Liu T, Milor L. Negative Bias Temperature Instability and Gate Oxide Breakdown Modeling in Circuits With Die-to-Die Calibration Through Power Supply and Ground Signal Measurements Ieee Transactions On Very Large Scale Integration Systems. 25: 2271-2284. DOI: 10.1109/Tvlsi.2017.2683261  0.453
2017 Zhang R, Liu T, Yang K, Milor L. Analysis of time-dependent dielectric breakdown induced aging of SRAM cache with different configurations Microelectronics Reliability. 87-91. DOI: 10.1016/J.Microrel.2017.06.040  0.416
2017 Kim DH, Milor L. Analysis of errors in estimating wearout characteristics of time-dependent dielectric breakdown using system-level accelerated life test Microelectronics Reliability. 47-52. DOI: 10.1016/J.Microrel.2017.06.039  0.385
2017 Yang K, Liu T, Zhang R, Kim DH, Milor L. Front-end of line and middle-of-line time-dependent dielectric breakdown reliability simulator for logic circuits Microelectronics Reliability. 81-86. DOI: 10.1016/J.Microrel.2017.06.038  0.416
2016 Chen C, Liu T, Milor L. System-Level Modeling of Microprocessor Reliability Degradation Due to Bias Temperature Instability and Hot Carrier Injection Ieee Transactions On Very Large Scale Integration Systems. 24: 2712-2725. DOI: 10.1109/Tvlsi.2016.2520658  0.392
2016 Kim W, Chen C, Kim D, Milor L. Built-In Self-Test Methodology With Statistical Analysis for Electrical Diagnosis of Wearout in a Static Random Access Memory Array Ieee Transactions On Very Large Scale Integration Systems. 24: 2521-2534. DOI: 10.1109/Tvlsi.2015.2513369  0.391
2015 Ahmed F, Milor L. Online Measurement of Degradation Due to Bias Temperature Instability in SRAMs Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. DOI: 10.1109/Tvlsi.2015.2500900  0.384
2015 Chen C, Milor L. Microprocessor Aging Analysis and Reliability Modeling Due to Back-End Wearout Mechanisms Ieee Transactions On Very Large Scale Integration Systems. 23: 2065-2076. DOI: 10.1109/Tvlsi.2014.2357756  0.385
2015 Bashir MM, Milor L. Impact of linewidth on backend dielectric TDDB and incorporation of the linewidth effect in full chip lifetime analysis Ieee Transactions On Semiconductor Manufacturing. 28: 25-34. DOI: 10.1109/Tsm.2014.2383832  0.648
2015 Liu T, Chen C, Kim W, Milor L. Comprehensive reliability and aging analysis on SRAMs within microprocessor systems Microelectronics Reliability. 55: 1290-1296. DOI: 10.1016/J.Microrel.2015.06.078  0.363
2015 Liu T, Chen C, Cha S, Milor L. System-level variation-aware aging simulator using a unified novel gate-delay model for bias temperature instability, hot carrier injection, and gate oxide breakdown Microelectronics Reliability. 55: 1334-1340. DOI: 10.1016/J.Microrel.2015.06.008  0.387
2015 Chen C, Liu T, Cha S, Milor L. Processor-level reliability simulator for time-dependent gate dielectric breakdown Microprocessors and Microsystems. 39: 950-960. DOI: 10.1016/J.Micpro.2015.10.002  0.423
2014 Bashir MM, Chen CC, Milor L, Kim DH, Lim SK. Backend dielectric reliability full chip simulator Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 22: 1750-1762. DOI: 10.1109/Tvlsi.2013.2277856  0.624
2013 Lv Z, Yang S, Wang H, Milor L. A Delay Evaluation Circuit for Analog BIST Function Ieice Transactions On Electronics. 96: 393-401. DOI: 10.1587/Transele.E96.C.393  0.339
2013 Milor L. Modeling Low-K Dielectric Breakdown in the Presence of Multiple Feature Geometries and Die-to-Die Linewidth Variation Ieee Design & Test of Computers. 1-1. DOI: 10.1109/Mdt.2009.131  0.422
2013 Chen C, Ahmed F, Milor L. Impact of NBTI/PBTIon SRAMs within microprocessor systems: Modeling, simulation, and analysis Microelectronics Reliability. 53: 1183-1188. DOI: 10.1016/J.Microrel.2013.06.003  0.361
2012 Ahmed F, Milor L. Analysis and On-Chip Monitoring of Gate Oxide Breakdown in SRAM Cells Ieee Transactions On Very Large Scale Integration Systems. 20: 855-864. DOI: 10.1109/Tvlsi.2011.2119500  0.386
2012 Chen C, Ahmed F, Kim DH, Lim SK, Milor L. Backend dielectric reliability simulator for microprocessor system Microelectronics Reliability. 52: 1953-1959. DOI: 10.1016/J.Microrel.2012.07.002  0.384
2011 Bashir MM, Milor L. Determining the impact of within-die variation on circuit timing Ieee Transactions On Semiconductor Manufacturing. 24: 385-391. DOI: 10.1109/Tsm.2011.2152865  0.619
2011 Bashir M, Milor L, Kim DH, Lim SK. Impact of irregular geometries on low-k dielectric breakdown Microelectronics Reliability. 51: 1582-1586. DOI: 10.1016/J.Microrel.2011.07.005  0.609
2010 Milor L, Hong C. Area Scaling for Backend Dielectric Breakdown Ieee Transactions On Semiconductor Manufacturing. 23: 429-441. DOI: 10.1109/Tsm.2010.2051730  0.566
2010 Ahmed F, Milor L. Via wearout detection with on-chip monitors Microelectronics Journal. 41: 789-800. DOI: 10.1016/J.Mejo.2010.01.006  0.392
2009 Jia C, Milor L. A DLL design for testing I/O setup and hold times Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 17: 1579-1592. DOI: 10.1109/Tvlsi.2008.2005522  0.582
2009 Bashir M, Milor L. Modeling Low-k Dielectric Breakdown to Determine Lifetime Requirements Ieee Design & Test of Computers. 26: 18-27. DOI: 10.1109/Mdt.2009.151  0.372
2009 Aftabjahani S, Milor L. Timing analysis with compact variation-aware standard cell models Integration. 42: 312-320. DOI: 10.1016/J.Vlsi.2008.11.008  0.623
2008 Jia C, Milor L. A BIST circuit for DLL fault detection Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 16: 1687-1695. DOI: 10.1109/Tvlsi.2008.2001732  0.557
2008 Choi M, Milor L. Diagnosis of Optical Lithography Faults With Product Test Sets Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 1657-1669. DOI: 10.1109/Tcad.2008.927672  0.337
2007 Milor L, Hong C. Backend dielectric breakdown dependence on linewidth and pattern density. Microelectronics Reliability. 47: 1473-1477. DOI: 10.1016/J.Microrel.2007.07.023  0.587
2007 Hong C, Milor L. Modeling of the breakdown mechanisms for porous copper/low-k process flows Microelectronics Reliability. 47: 1478-1482. DOI: 10.1016/J.Microrel.2007.07.020  0.569
2006 Choi M, Milor L. Impact on circuit performance of deterministic within-die variation in nanoscale semiconductor manufacturing Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 1350-1367. DOI: 10.1109/Tcad.2005.855963  0.526
2004 Orshansky M, Milor L, Hu C. Characterization of spatial intrafield gate CD variability, its impact on circuit performance, and spatial mask-level correction Ieee Transactions On Semiconductor Manufacturing. 17: 2-11. DOI: 10.1109/Tsm.2003.822735  0.351
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