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Trevor N. Mudge - Publications

Affiliations: 
University of Michigan, Ann Arbor, Ann Arbor, MI 
Area:
Electronics and Electrical Engineering, Computer Science
Website:
https://eecs.engin.umich.edu/people/mudge-trevor/
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88 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Park D, Pal S, Feng S, Gao P, Tan J, Rovinski A, Xie S, Zhao C, Amarnath A, Wesley T, Beaumont J, Chen K, Chakrabarti C, Taylor MB, Mudge T, et al. A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix–Matrix Multiplication Accelerator Ieee Journal of Solid-State Circuits. 55: 933-944. DOI: 10.1109/Jssc.2019.2960480  0.769
2019 Chen H, Lee S, Mudge T, Wu C, Chakrabarti C. Configurable-ECC: Architecting a Flexible ECC Scheme to Support Different Sized Accesses in High Bandwidth Memory Systems Ieee Transactions On Computers. 68: 646-659. DOI: 10.1109/Tc.2018.2886884  0.377
2017 Pinckney N, Jeloka S, Dreslinski R, Mudge T, Sylvester D, Blaauw D, Shifren L, Cline B, Sinha S. Impact of FinFET on Near-Threshold Voltage Scalability Ieee Design & Test. 34: 31-38. DOI: 10.1109/Mdat.2016.2630303  0.684
2016 Hauswald J, Laurenzano MA, Zhang Y, Yang H, Kang Y, Li C, Rovinski A, Khurana A, Dreslinski RG, Mudge T, Petrucci V, Tang L, Mars J. Designing future warehouse-scale computers for sirius, an end-to-end voice and vision personal assistant Acm Transactions On Computer Systems. 34. DOI: 10.1145/2870631  0.693
2016 Chen H, Jeloka S, Arunkumar A, Blaauw D, Wu C, Mudge T, Chakrabarti C. Using Low Cost Erasure and Error Correction Schemes to Improve Reliability of Commodity DRAM Systems Ieee Transactions On Computers. 65: 3766-3779. DOI: 10.1109/Tc.2016.2550455  0.324
2016 Hauswald J, Laurenzano MA, Zhang Y, Li C, Rovinski A, Khurana A, Dreslinski RG, Mudge T, Petrucci V, Tang L, Mars J. Sirius Implications for Future Warehouse-Scale Computers Ieee Micro. 36: 42-53. DOI: 10.1109/Mm.2016.37  0.654
2016 Chen Y, Chiotellis N, Chuo L, Pfeiffer C, Shi Y, Dreslinski RG, Grbic A, Mudge T, Wentzloff DD, Blaauw D, Kim HS. Energy-Autonomous Wireless Communication for Millimeter-Scale Internet-of-Things Sensor Nodes Ieee Journal On Selected Areas in Communications. 34: 3962-3977. DOI: 10.1109/Jsac.2016.2612041  0.655
2016 Chen Y, Lu S, Kim HS, Blaauw D, Dreslinski RG, Mudge T. A low power software-defined-radio baseband processor for the Internet of Things Proceedings - International Symposium On High-Performance Computer Architecture. 2016: 40-51. DOI: 10.1109/HPCA.2016.7446052  0.697
2015 Mudge T. The specialization trend in computer hardware Communications of the Acm. 58: 84. DOI: 10.1145/2735839  0.32
2014 Gutierrez A, Dreslinski RG, Mudge T. Evaluating private vs. shared last-level caches for energy efficiency in asymmetric multi-cores Proceedings - International Conference On Embedded Computer Systems: Architectures, Modeling and Simulation, Samos 2014. 191-198. DOI: 10.1109/SAMOS.2014.6893211  0.66
2014 Hauswald J, Manville T, Zheng Q, Dreslinski R, Chakrabarti C, Mudge T. A hybrid approach to offloading mobile image classification Icassp, Ieee International Conference On Acoustics, Speech and Signal Processing - Proceedings. 8375-8379. DOI: 10.1109/ICASSP.2014.6855235  0.635
2013 Dreslinski RG, Fick D, Giridhar B, Kim G, Seo S, Fojtik M, Satpathy S, Lee Y, Kim D, Liu N, Wieckowski M, Chen G, Sylvester D, Blaauw D, Mudge T. Centip3De: A many-core prototype exploring 3d integration and near-threshold computing Communications of the Acm. 56: 97-104. DOI: 10.1145/2524713.2524725  0.743
2013 Pinckney N, Dreslinski RG, Sewell K, Fick D, Mudge T, Sylvester D, Blaauw D. Limits of parallelism and boosting in dim silicon Ieee Micro. 33: 30-37. DOI: 10.1109/Mm.2013.73  0.789
2013 Dreslinski RG, Fick D, Giridhar B, Kim G, Seo S, Fojtik M, Satpathy S, Lee Y, Kim D, Liu N, Wieckowski M, Chen G, Sylvester D, Blaauw D, Mudge T. Centip3De: A 64-Core, 3D stacked near-threshold system Ieee Micro. 33: 8-16. DOI: 10.1109/Mm.2013.4  0.736
2013 Fick D, Dreslinski RG, Giridhar B, Kim G, Seo S, Fojtik M, Satpathy S, Lee Y, Kim D, Liu N, Wieckowski M, Chen G, Mudge T, Blaauw D, Sylvester D. Centip3De: A cluster-based NTC architecture with 64 ARM cortex-M3 cores in 3D stacked 130 nm CMOS Ieee Journal of Solid-State Circuits. 48: 104-117. DOI: 10.1109/Jssc.2012.2222814  0.737
2012 Gutierrez A, Pusdesris J, Dreslinski RG, Mudge T. Lazy cache invalidation for self-modifying codes Cases'12 - Proceedings of the 2012 Acm International Conference On Compilers, Architectures and Synthesis For Embedded Systems, Co-Located With Esweek. 151-160. DOI: 10.1145/2380403.2380433  0.643
2012 Hormati A, Samadi M, Woh M, Mudge T, Mahlke S. Sponge: Portable stream programming on graphics engines Acm Sigplan Notices. 47: 381-392. DOI: 10.1145/2248487.1950409  0.773
2012 Sethia A, Dasika G, Mudge T, Mahlke S. A customized processor for energy efficient scientific computing Ieee Transactions On Computers. 61: 1711-1723. DOI: 10.1109/Tc.2012.144  0.456
2012 Sewell K, Dreslinski RG, Manville T, Satpathy S, Pinckney N, Blake G, Cieslak M, Das R, Wenisch TF, Sylvester D, Blaauw D, Mudge T. Swizzle-switch networks for many-core systems Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 2: 278-294. DOI: 10.1109/Jetcas.2012.2193936  0.791
2011 Dasika G, Sethia A, Mudge T, Mahlke S. PEPSC: A power-efficient processor for scientific computing Parallel Architectures and Compilation Techniques - Conference Proceedings, Pact. 100-110. DOI: 10.1109/PACT.2011.16  0.346
2011 Blake G, Dreslinski RG, Mudge T. Bloom filter guided transaction scheduling Proceedings - International Symposium On High-Performance Computer Architecture. 75-86. DOI: 10.1109/HPCA.2011.5749718  0.549
2011 Woh M, Lin Y, Seo S, Mahlke S, Mudge T. Analyzing the next generation software defined radio for future architectures Journal of Signal Processing Systems. 63: 83-94. DOI: 10.1007/s11265-009-0402-z  0.785
2011 Satpathy S, Dreslinski R, Ou TC, Sylvester D, Mudge T, Blaauw D. SWIFT: A 2.1Tb/s 32x32 self-arbitrating manycore interconnect fabric Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 138-139.  0.561
2010 Blake G, Dreslinski RG, Mudge T, Flautner K. Evolution of thread-level parallelism in desktop applications Proceedings - International Symposium On Computer Architecture. 302-313. DOI: 10.1145/1815961.1816000  0.778
2010 Wieckowski M, Dreslinski RG, Mudge T, Blaauw D, Sylvester D. Circuit design advances for ultra-low power sensing platforms Proceedings of Spie - the International Society For Optical Engineering. 7679. DOI: 10.1117/12.850720  0.701
2010 Chen G, Sylvester D, Blaauw D, Mudge T. Yield-driven near-threshold SRAM design Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 18: 1590-1598. DOI: 10.1109/Tvlsi.2009.2025766  0.361
2010 Lee H, Chakrabarti C, Mudge T. A low-power DSP for wireless communications Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 18: 1310-1322. DOI: 10.1109/Tvlsi.2009.2023547  0.47
2010 Woh M, Seo S, Mahlke S, Mudge T, Chakrabarti C, Flautner K. AnySP: Anytime anywhere anyway signal processing Ieee Micro. 30: 81-91. DOI: 10.1109/Mm.2010.8  0.787
2010 Mudge T, Holzle U. Challenges and opportunities for extremely energy-efficient processors Ieee Micro. 30: 20-22. DOI: 10.1109/Mm.2010.61  0.383
2010 Mudge T. Guest editor's introduction: Top picks from the computer architecture conferences of 2009 Ieee Micro. 30: 8-11. DOI: 10.1109/Mm.2010.19  0.345
2010 Woh M, Mahlke S, Mudge T, Chakrabarti C. Mobile supercomputers for the next-generation cell phone Computer. 43: 81-85. DOI: 10.1109/Mc.2010.16  0.782
2010 Woh M, Seo S, Chakrabarti C, Mahlke S, Mudge T. An ultra low power SIMD processor for wireless devices Conference Record - Asilomar Conference On Signals, Systems and Computers. 390-394. DOI: 10.1109/ACSSC.2010.5757542  0.796
2009 Blake G, Dreslinski RG, Mudge T. Proactive transaction scheduling for contention management Proceedings of the Annual International Symposium On Microarchitecture, Micro. 156-167. DOI: 10.1145/1669112.1669133  0.647
2009 Roberts D, Kgil T, Mudge T. Integrating NAND flash devices onto servers Communications of the Acm. 52: 98-106. DOI: 10.1145/1498765.1498791  0.397
2009 Blake G, Dreslinski RG, Mudge T. A survey of multicore processors: A review of their common attributes Ieee Signal Processing Magazine. 26: 26-37. DOI: 10.1109/Msp.2009.934110  0.705
2009 Lim K, Ranganathan P, Chang J, Patel C, Mudge T, Reinhardt SK. Server designs for warehouse-computing environments Ieee Micro. 29: 41-49. DOI: 10.1109/Mm.2009.14  0.391
2008 Kgil T, Saidi A, Binkert N, Reinhardt S, Flautner K, Mudge T. PicoServer: Using 3D stacking technology to build energy efficient servers Acm Journal On Emerging Technologies in Computing Systems. 4. DOI: 10.1145/1412587.1412589  0.702
2008 Karl E, Blaauw D, Sylvester D, Mudge T. Multi-mechanism reliability modeling and management in dynamic systems Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 16: 476-487. DOI: 10.1109/Tvlsi.2007.915477  0.354
2008 Kgil T, Roberts D, Mudge T. Improving NAND flash based disk caches Proceedings - International Symposium On Computer Architecture. 327-338. DOI: 10.1109/ISCA.2008.32  0.32
2008 Who M, Lin Y, Seo S, Mudge T, Mahlke S. Analyzing the scalability of SIMD for the next generation software defined radio Icassp, Ieee International Conference On Acoustics, Speech and Signal Processing - Proceedings. 5388-5391. DOI: 10.1109/ICASSP.2008.4518878  0.317
2008 Roberts D, Kim NS, Mudge T. On-chip cache device scaling limits and effective fault repair techniques in future nanoscale technology Microprocessors and Microsystems. 32: 244-253. DOI: 10.1016/J.Micpro.2008.03.012  0.366
2008 Özer E, Dreslinski RG, Mudge T, Biles S, Flautner K. Energy-efficient simultaneous thread fetch from different cache levels in a soft real-time SMT processor Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 5114: 12-22. DOI: 10.1007/978-3-540-70550-5_3  0.773
2007 Lin Y, Kudlur M, Mahlke S, Mudge T. Hierarchical coarse-grained stream compilation for software defined radio Cases'07: Proceedings of the 2007 International Conference On Compilers, Architecture, and Synthesis For Embedded Systems. 115-124. DOI: 10.1145/1289881.1289903  0.312
2007 Dreslinski RG, Saidi AG, Mudge T, Reinhardt SK. Analysis of hardware prefetching across virtual page boundaries 2007 Computing Frontiers, Conference Proceedings. 13-22. DOI: 10.1145/1242531.1242537  0.575
2007 Lin Y, Lee H, Woh M, Harel Y, Mahlke S, Mudge T, Chakrabarti C, Flautner K. SODA: A high-performance DSP architecture for software-defined radio Ieee Micro. 27: 114-123. DOI: 10.1109/Mm.2007.22  0.791
2006 Jerraya A, Mudge T. Guest editorial: Concurrent hardware and software design for multiprocessor SoC Acm Transactions in Embedded Computing Systems. 5: 259-262. DOI: 10.1145/1151074.1151075  0.31
2006 Das S, Roberts D, Lee S, Pant S, Blaauw D, Austin T, Flautner K, Mudge T. A self-tuning DVS processor using delay-error detection and correction Ieee Journal of Solid-State Circuits. 41: 792-804. DOI: 10.1109/Jssc.2006.870912  0.684
2005 Kgil T, Falk L, Mudge T. ChipLock: support for secure microarchitectures Acm Sigarch Computer Architecture News. 33: 134-143. DOI: 10.1145/1055626.1055644  0.382
2005 Kim NS, Blaauw D, Mudge T. Quantitative analysis and optimization techniques for on-chip cache leakage power Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 13: 1147-1156. DOI: 10.1109/Tvlsi.2005.859476  0.415
2005 Kim NS, Flautner K, Blaauw D, Mudge T. Erratum: Circuit and microarchitectural techniques for reducing cache leakage power (IEEE Transactions on Very Large Scale Integration (VLSI) Systems (Feb. 2004) 12:2 (167-184)) Ieee Transactions On Very Large Scale Integration Systems. 13. DOI: 10.1109/Tvlsi.2005.845312  0.698
2005 Oehmke DW, Binkert NL, Mudge T, Reinhardt SK. How to fake 1000 registers Proceedings of the Annual International Symposium On Microarchitecture, Micro. 7-18. DOI: 10.1109/MICRO.2005.21  0.712
2005 Roberts D, Austin T, Blauww D, Mudge T, Flautner K. Error analysis for the support of robust voltage scaling Proceedings - International Symposium On Quality Electronic Design, Isqed. 65-70. DOI: 10.1109/ISQED.2005.53  0.649
2005 Cheng AC, Tyson GS, Mudge TN. PowerFITS: Reduce dynamic and static i-cache power using application specific instruction set synthesis Ispass 2005 - Ieee International Symposium On Performance Analysis of Systems and Software. 2005: 32-41. DOI: 10.1109/ISPASS.2005.1430557  0.345
2005 Bai R, Kim NS, Kgil TH, Sylvester D, Mudge T. Power-performance trade-offs in nanometer-scale multi-level caches considering total leakage Proceedings -Design, Automation and Test in Europe, Date '05. 650-651. DOI: 10.1109/DATE.2005.243  0.737
2004 Kim NS, Flautner K, Blaauw D, Mudge T. Circuit and Microarchitectural Techniques for Reducing Cache Leakage Power Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 12: 167-184. DOI: 10.1109/Tvlsl.2003.821550  0.719
2004 Ernst D, Das S, Lee S, Blaauw D, Austin T, Mudge T, Kim NS, Flautner K. Razor: Circuit-level correction of timing errors for low-power operation Ieee Micro. 24: 10-20. DOI: 10.1109/Mm.2004.85  0.693
2004 Austin T, Blaauw D, Mahlke S, Mudge T, Chakrabarti C, Wolf W. Mobile supercomputers Computer. 37: 81-83. DOI: 10.1109/Mc.2004.1297253  0.413
2004 Austin T, Blaauw D, Mudge T, Flautner K. Making typical silicon matter with razor Computer. 37: 57-65. DOI: 10.1109/Mc.2004.1274005  0.723
2004 Kim NS, Flautner K, Blaauw D, Mudge T. Single-VDD and Single-VT Super-Drowsy Techniques for Low-Leakage High-Performance Instruction Caches Proceedings of the International Symposium On Low Power Electronics and Design. 2004: 54-57. DOI: 10.1109/LPE.2004.240783  0.682
2004 Kim NS, Flautner K, Blaauw D, Mudge T. Single-V DD and single-V T super-drowsy techniques for low-leakage high-performance instruction caches Proceedings of the 2004 International Symposium On Lower Power Electronics and Design, Islped'04. 54-57.  0.683
2003 Kim NS, Austin T, Blaauw D, Mudge T, Flautner K, Hu JS, Jane Irwin M, Kandemir M, Narayanan V. Leakage Current: Moore's Law Meets Static Power Computer. 36. DOI: 10.1109/Mc.2003.1250885  0.691
2002 Flautner K, Mudge T. Vertigo: Automatic performance-setting for linux+ Operating Systems Review (Acm). 36: 105-116. DOI: 10.1145/844128.844139  0.691
2002 Martin SM, Flautner K, Mudge T, Blaauw D. Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 721-725. DOI: 10.1145/774572.774678  0.689
2002 Blaauw D, Martin S, Mudge T, Flautner K. Leakage current reduction in VLSI systems Journal of Circuits, Systems and Computers. 11: 621-635. DOI: 10.1142/S0218126602000665  0.678
2002 Kim NS, Flautner K, Blaauw D, Mudge T. Drowsy instruction caches. Leakage power reduction using dynamic voltage scaling and cache sub-bank prediction Proceedings of the Annual International Symposium On Microarchitecture, Micro. 2002: 219-230. DOI: 10.1109/MICRO.2002.1176252  0.71
2002 Flautner K, Kim NS, Martin S, Blaauw D, Mudge T. Drowsy caches: Simple techniques for reducing leakage power Conference Proceedings - Annual International Symposium On Computer Architecture, Isca. 148-157.  0.696
2001 Mudge T. Power: A first-class architectural design constraint Computer. 34: 52-58. DOI: 10.1109/2.917539  0.42
2001 Cuppu V, Jacob B, Davis B, Mudge T. High-performance DRAMs in workstation environments Ieee Transactions On Computers. 50: 1133-1153. DOI: 10.1109/12.966491  0.662
2001 Jacob B, Mudge T. Uniprocessor virtual memory without TLBs Ieee Transactions On Computers. 50: 482-499. DOI: 10.1109/12.926161  0.644
2001 Flautner K, Reinhardt S, Mudge T. Automatic performance setting for dynamic voltage scaling Proceedings of the Annual International Conference On Mobile Computing and Networking, Mobicom. 260-271. DOI: 10.1023/A:1016546330128  0.713
2001 Flautner K, Reinhardt S, Mudge T. Automatic performance setting for dynamic voltage scaling Proceedings of the Annual International Conference On Mobile Computing and Networking, Mobicom. 260-271. DOI: 10.1023/A:1016546330128  0.691
2000 Eden AN, Joh BW, Mudge T. Web latency reduction via client-side prefetching 2000 Ieee International Symposium On Performance Analysis of Systems and Software, Ispass 2000. 193-200. DOI: 10.1109/ISPASS.2000.842300  0.681
2000 Van Campenhout D, Mudge T, Hayes JP. Collection and analysis of microprocessor design errors Ieee Design and Test of Computers. 17: 51-60. DOI: 10.1109/54.895006  0.522
2000 Davis B, Jacob B, Mudge T. The new DRAM interfaces: SDRAM, RDRAM and variants Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 1940: 26-31.  0.585
2000 Flautner K, Uhlig R, Reinhardt S, Mudge T. Thread-level parallelism and interactive performance of desktop applications International Conference On Architectural Support For Programming Languages and Operating Systems - Asplos. 129-138.  0.675
1999 Flautner K, Tyson GS, Mudge T. A high level simulator integrated with the Mirv compiler Acm Sigarch Computer Architecture News. 27: 43-46. DOI: 10.1145/309758.309778  0.654
1998 Campenhout DV, Al-Asaad H, Hayes JP, Mudge T, Brown RB. High-level design verification of microprocessors via error modeling Acm Transactions On Design Automation of Electronic Systems (Todaes). 3: 581-599. DOI: 10.1145/296333.296347  0.518
1998 Jacob B, Mudge T. Virtual memory in contemporary microprocessors Ieee Micro. 18: 60-75. DOI: 10.1109/40.710872  0.606
1998 Jacob B, Mudge T. Virtual memory: Issues of implementation Computer. 31: 33-43. DOI: 10.1109/2.683005  0.605
1998 Jacob BL, Mudge TN. A Look at Several Memory Management Units, TLB-Refill Mechanisms, and Page Table Organizations Operating Systems Review (Acm). 32: 295-306.  0.59
1998 Eden AN, Mudge T. YAGS branch prediction scheme Proceedings of the Annual International Symposium On Microarchitecture. 69-77.  0.662
1997 Uhlig R, Nagle D, Mudge T, Sechrest S. Trap-driven memory simulation with Tapeworm II Acm Transactions On Modeling and Computer Simulation. 7: 7-41. DOI: 10.1145/244804.244805  0.304
1996 Mudge T. Strategic directions in computer architecture Acm Computing Surveys. 28: 671-678. DOI: 10.1145/242223.242271  0.359
1994 Uhlig R, Nagle D, Stanley T, Mudge T, Sechrest S, Brown R. Design Tradeoffs for Software-Managed TLBs Acm Transactions On Computer Systems (Tocs). 12: 175-205. DOI: 10.1145/185514.185515  0.339
1993 Sakallah KA, Mudge TN, Burks TM, Davidson ES. Synchronization of Pipelines Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 12: 1132-1146. DOI: 10.1109/43.238606  0.574
1989 Clapp R, Mudge T. Ada on a hypercube Acm Sigada Ada Letters. 118-128. DOI: 10.1145/66031.66040  0.308
1986 Hayes JP, Mudge T, Stout QF, Colley S, Palmer J. A Microprocessor-based Hypercube Supercomputer Ieee Micro. 6: 6-17. DOI: 10.1109/Mm.1986.304707  0.533
1986 Mudge TN, Hayes JP, Buzzard GD, Winsor DC. Analysis of multiple-bus interconnection networks Journal of Parallel and Distributed Computing. 3: 328-343. DOI: 10.1016/0743-7315(86)90019-5  0.499
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