| Year |
Citation |
Score |
| 2015 |
Al-Khaleel O, Al-Qudah Z, Al-Khaleel M, Bani-Hani R, Papachristou CA, Wolff FG. Efficient Hardware Implementations of Binary-to-BCD Conversion Schemes for Decimal Multiplication Journal of Circuits, Systems, and Computers. 24: 1550019. DOI: 10.1142/S021812661550019X |
0.692 |
|
| 2013 |
Narasimhan S, Du D, Chakraborty RS, Paul S, Wolff FG, Papachristou CA, Roy K, Bhunia S. Hardware trojan detection by multiple-parameter side-channel analysis Ieee Transactions On Computers. 62: 2183-2195. DOI: 10.1109/Tc.2012.200 |
0.728 |
|
| 2013 |
Al-Khaleel O, Al-Qudah Z, Al-Khaleel M, Papachristou CA. High performance FPGA-based decimal-to-binary conversion schemes for decimal arithmetic Microprocessors and Microsystems. 37: 287-298. DOI: 10.1016/J.Micpro.2013.01.002 |
0.753 |
|
| 2011 |
Al-Omari H, Papachristou C, Wolff F, Mcintyre D. Smoothing delay jitter in networked control systems Journal of Embedded Computing. 4: 11-21. DOI: 10.3233/Jec-2009-0103 |
0.696 |
|
| 2011 |
Al-Khaleel O, Al-Khaleel M, Al-Qudahj Z, Papachristou CA, Mhaidat K, Wolff FG. Fast binary/decimal adder/subtractor with a novel correction-free BCD addition 2011 18th Ieee International Conference On Electronics, Circuits, and Systems, Icecs 2011. 455-459. DOI: 10.1109/ICECS.2011.6122311 |
0.737 |
|
| 2011 |
Al-Khaleel O, Al-Qudah Z, Al-Khaleel M, Papachristou CA, Wolff FG. Fast and compact binary-to-BCD conversion circuits for decimal multiplication Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 226-231. DOI: 10.1109/ICCD.2011.6081401 |
0.735 |
|
| 2003 |
Knieser MJ, Wolff FG, Papachristou CA, Weyer DJ, McIntyre DR. A technique for high ratio LZW compression Proceedings -Design, Automation and Test in Europe, Date. 116-121. DOI: 10.1109/DATE.2003.1253596 |
0.658 |
|
| 2002 |
Nourani M, Papachristou CA. False path exclusion in delay analysis of RTL structures Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 10: 30-43. DOI: 10.1109/92.988728 |
0.348 |
|
| 2001 |
Nourani M, Carletta J, Papachristou C. Integrated test of interacting controllers and datapaths Acm Transactions On Design Automation of Electronic Systems. 6: 401-422. DOI: 10.1145/383251.383258 |
0.319 |
|
| 2000 |
Nourani M, Papachristou C. Stability-based algorithms for high-level synthesis of digital ASICs Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 8: 431-435. DOI: 10.1109/92.863623 |
0.346 |
|
| 1999 |
Papachristou CA, Nourani M, Spining M. A multiple clocking scheme for low-power RTL design Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 7: 266-276. DOI: 10.1109/92.766754 |
0.369 |
|
| 1999 |
Nourani M, Papachristou CA. Structural fault testing of embedded cores using pipelining Journal of Electronic Testing: Theory and Applications (Jetta). 15: 129-144. DOI: 10.1023/A:1008340519743 |
0.34 |
|
| 1998 |
Ockunzzi KA, Papachristou CA. Testability Enhancement for Control-Flow Intensive Behaviors Journal of Electronic Testing: Theory and Applications (Jetta). 13: 239-257. DOI: 10.1023/A:1008381718989 |
0.667 |
|
| 1998 |
Papachristou CA, Baklashov M, Lai K. High-Level Test Synthesis for Behavioral and Structural Designs Journal of Electronic Testing: Theory and Applications (Jetta). 13: 167-188. DOI: 10.1023/A:1008309921888 |
0.409 |
|
| 1997 |
Carletta JE, Papachristou CA. Behavioral Testability Insertion for Datapath/Controller Circuits Journal of Electronic Testing: Theory and Applications (Jetta). 11: 9-28. DOI: 10.1023/A:1008291616071 |
0.381 |
|
| 1995 |
Jone W, Papachristou CA. A coordinated circuit partitioning and test generation method for pseudo-exhaustive testing of VLSI circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 14: 374-384. DOI: 10.1109/43.365128 |
0.461 |
|
| 1993 |
Papachristou CA, Immaneni VR. Vertical Migration of Software Functions and Algorithms Using Enhanced Microsequencing Ieee Transactions On Computers. 42: 45-61. DOI: 10.1109/12.192213 |
0.405 |
|
| 1992 |
Koutsougeras C, Georgiou G, Papachristou CA. A feedforward neural network classifier model: multiple classes, confidence output values, and implementation International Journal of Pattern Recognition and Artificial Intelligence. 6: 539-569. DOI: 10.1142/S0218001492000308 |
0.317 |
|
| 1991 |
Papachristou CA, Gambhir SB. Microcontrol architectures with sequencing firmware and modular microcode development tools Microprocessing and Microprogramming. 29: 303-328. DOI: 10.1016/0165-6074(91)90005-E |
0.437 |
|
| 1990 |
Papachristou CA, Pandya AL. A Design Scheme for PLA-Based Control Tables with Reduced Area and Time-Delay Cost Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 9: 453-472. DOI: 10.1109/43.55178 |
0.356 |
|
| 1989 |
Jone WB, Papachristou CA, Pereira M. Scheme for overlaying concurrent testing of VLSI circuits Proceedings - Design Automation Conference. 531-536. |
0.312 |
|
| 1988 |
Jone WB, Papachristou CA. On partitioning for pseudo exhaustive testing of VLSI circuits Proceedings - Ieee International Symposium On Circuits and Systems. 2: 1843-1846. |
0.363 |
|
| 1986 |
Koutsougeras C, Papachristou CA, Vemuri RR. DATA FLOW GRAPH PARTITIONING TO REDUCE COMMUNICATION COST Micro: Annual Microprogramming Workshop. 82-91. |
0.501 |
|
| 1985 |
Papachristou CA, Cornett D. Generation and implementation of state machine controllers: A VLSI approach Microprocessing and Microprogramming. 16: 73-81. DOI: 10.1016/0165-6074(85)90042-0 |
0.36 |
|
| 1984 |
Papachristou CA. A PLA microcontroller using horizontal firmware Microprocessing and Microprogramming. 14: 223-230. DOI: 10.1016/0165-6074(84)90024-3 |
0.394 |
|
| 1978 |
Papachristou CA. MODULAR LOGIC DESIGN WITH NAND CASCADES OF INTEGRATED CIRCUITS Digital Processes. 4: 273-294. |
0.31 |
|
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