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Sarma Vrudhula - Publications

Affiliations: 
University of Arizona, Tucson, AZ 
Area:
Electronics and Electrical Engineering, Computer Science
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57 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Azari E, Vrudhula S. ELSA Acm Transactions On Embedded Computing Systems. 19: 1-21. DOI: 10.1145/3366634  0.422
2020 Ma Y, Cao Y, Vrudhula S, Seo J. Performance Modeling for CNN Inference Accelerators on FPGA Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 39: 843-856. DOI: 10.1109/Tcad.2019.2897634  0.449
2020 Ma Y, Cao Y, Vrudhula S, Seo J. Automatic Compilation of Diverse CNNs Onto High-Performance FPGA Accelerators Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 39: 424-437. DOI: 10.1109/Tcad.2018.2884972  0.44
2019 Gaudette B, Wu C, Vrudhula S. Optimizing User Satisfaction of Mobile Workloads Subject to Various Sources of Uncertainties Ieee Transactions On Mobile Computing. 18: 2941-2953. DOI: 10.1109/Tmc.2018.2883619  0.413
2018 Ma Y, Cao Y, Vrudhula S, Seo J. Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 26: 1354-1367. DOI: 10.1109/Tvlsi.2018.2815603  0.396
2018 Yang J, Dengi A, Vrudhula S. Design Considerations for Energy-Efficient and Variation-Tolerant Nonvolatile Logic Ieee Transactions On Very Large Scale Integration Systems. 26: 2628-2640. DOI: 10.1109/Tvlsi.2018.2812700  0.492
2018 Ma Y, Suda N, Cao Y, Vrudhula S, Seo J. ALAMO: FPGA acceleration of deep learning algorithms with a modularized RTL compiler Integration. 62: 14-23. DOI: 10.1016/J.Vlsi.2017.12.009  0.324
2016 Suda N, Chandra V, Dasika G, Mohanty A, Ma Y, Vrudhula S, Seo JS, Cao Y. Throughput-optimized openCL-based FPGA accelerator for large-scale convolutional neural networks Fpga 2016 - Proceedings of the 2016 Acm/Sigda International Symposium On Field-Programmable Gate Arrays. 16-25. DOI: 10.1145/2847263.2847276  0.344
2016 Kulkarni N, Yang J, Seo JS, Vrudhula S. Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. DOI: 10.1109/Tvlsi.2016.2527783  0.398
2016 Gaudette B, Wu CJ, Vrudhula S. Improving smartphone user experience by balancing performance and energy with probabilistic QoS guarantee Proceedings - International Symposium On High-Performance Computer Architecture. 2016: 52-63. DOI: 10.1109/HPCA.2016.7446053  0.34
2015 Gao L, Wang IT, Chen PY, Vrudhula S, Seo JS, Cao Y, Hou TH, Yu S. Fully parallel write/read in resistive synaptic array for accelerating on-chip learning. Nanotechnology. 26: 455204. PMID 26491032 DOI: 10.1088/0957-4484/26/45/455204  0.365
2015 Seo JS, Lin B, Kim M, Chen PY, Kadetotad D, Xu Z, Mohanty A, Vrudhula S, Yu S, Ye J, Cao Y. On-Chip Sparse Learning Acceleration With CMOS and Resistive Synaptic Devices Ieee Transactions On Nanotechnology. 14: 969-979. DOI: 10.1109/Tnano.2015.2478861  0.402
2015 Mahalanabis D, Bharadwaj V, Barnaby HJ, Vrudhula S, Kozicki MN. A nonvolatile sense amplifier flip-flop using programmable metallization cells Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 5: 205-213. DOI: 10.1109/Jetcas.2015.2433571  0.442
2015 Kadetotad D, Xu Z, Mohanty A, Chen PY, Lin B, Ye J, Vrudhula S, Yu S, Cao Y, Seo Js. Parallel Architecture With Resistive Crosspoint Array for Dictionary Learning Acceleration Ieee Journal On Emerging and Selected Topics in Circuits and Systems. DOI: 10.1109/Jetcas.2015.2426495  0.378
2015 Kulkarni N, Yang J, Vrudhula S. A fast, energy efficient, field programmable threshold-logic array Proceedings of the 2014 International Conference On Field-Programmable Technology, Fpt 2014. 300-305. DOI: 10.1109/FPT.2014.7082804  0.321
2015 Winther AT, Liu W, Nannarelli A, Vrudhula S. Thermal aware floorplanning incorporating temperature dependent wire delay estimation Microprocessors and Microsystems. 39: 807-815. DOI: 10.1016/J.Micpro.2015.09.013  0.301
2014 Xu Z, Cavaliere M, An P, Vrudhula S, Cao Y. The stochastic loss of spikes in spiking neural P systems: Design and implementation of reliable arithmetic circuits Fundamenta Informaticae. 134: 183-200. DOI: 10.3233/Fi-2014-1098  0.322
2014 Hanumaiah V, Desai D, Gaudette B, Wu CJ, Vrudhula S. STEAM: A smart temperature and energy aware multicore controller Acm Transactions On Embedded Computing Systems. 13. DOI: 10.1145/2661430  0.484
2014 Gaudette B, Hanumaiah V, Krunz M, Vrudhula S. Maximizing Quality of Coverage under Connectivity Constraints in Solar-Powered Active Wireless Sensor Networks Acm Transactions On Sensor Networks. 10: 59. DOI: 10.1145/2594792  0.383
2014 Mahalanabis D, Gonzalez-Velo Y, Barnaby HJ, Kozicki MN, Dandamudi P, Vrudhula S. Impedance measurement and characterization of Ag-Ge30Se70-based programmable metallization cells Ieee Transactions On Electron Devices. 61: 3723-3730. DOI: 10.1109/Ted.2014.2358573  0.327
2014 Hanumaiah V, Vrudhula S. Energy-efficient operation of multicore processors by DVFS, task migration, and active cooling Ieee Transactions On Computers. 63: 349-360. DOI: 10.1109/Tc.2012.213  0.478
2014 Yang J, Kulkarni N, Yu S, Vrudhula S. Integration of threshold logic gates with RRAM devices for energy efficient and robust operation Proceedings of the 2014 Ieee/Acm International Symposium On Nanoscale Architectures, Nanoarch 2014. 39-44. DOI: 10.1109/NANOARCH.2014.6880500  0.336
2012 Hanumaiah V, Vrudhula S. Temperature-aware DVFS for hard real-time applications on multicore processors Ieee Transactions On Computers. 61: 1484-1494. DOI: 10.1109/Tc.2011.156  0.39
2011 Hanumaiah V, Vrudhula S, Chatha KS. Performance optimal online DVFS and task migration techniques for thermally constrained multi-core processors Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 30: 1677-1690. DOI: 10.1109/Tcad.2011.2161308  0.375
2011 Gowda T, Vrudhula S, Kulkarni N, Berezowski K. Identification of threshold functions and synthesis of threshold networks Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 30: 665-677. DOI: 10.1109/Tcad.2010.2100232  0.307
2010 Shrivastava A, Kannan D, Bhardwaj S, Vrudhula S. Reducing functional unit power consumption and its variation using leakage sensors Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 18: 988-997. DOI: 10.1109/Tvlsi.2009.2019082  0.405
2010 Wang W, Yang S, Bhardwaj S, Vrudhula S, Liu F, Cao Y. The impact of NBTI effect on combinational circuit: Modeling, simulation, and analysis Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 18: 173-183. DOI: 10.1109/Tvlsi.2008.2008810  0.356
2009 Gowda T, Vrudhula S, Kim S. Prediction of pairwise gene interaction using threshold logic. Annals of the New York Academy of Sciences. 1158: 276-86. PMID 19348649 DOI: 10.1111/J.1749-6632.2008.03763.X  0.314
2009 Zhuo J, Chakrabarti C, Lee K, Chang N, Vrudhula S. Maximizing the lifetime of embedded systems powered by fuel cell-battery hybrids Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 17: 22-32. DOI: 10.1109/Tvlsi.2008.2008432  0.485
2009 Goel A, Vrudhula S, Taraporevala F, Ghanta P. Statistical timing models for large macro cells and IP blocks considering process variations Ieee Transactions On Semiconductor Manufacturing. 22: 3-11. DOI: 10.1109/Tsm.2008.2011629  0.389
2009 Rao R, Vrudhula S. Fast and accurate prediction of the steady-state throughput of multicore processors under thermal constraints Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 28: 1559-1572. DOI: 10.1109/Tcad.2009.2026361  0.398
2008 Lee K, Chang N, Zhuo J, Chakrabarti C, Kadri S, Vrudhula S. A fuel-cell-battery hybrid for portable embedded systems Acm Transactions On Design Automation of Electronic Systems. 13. DOI: 10.1145/1297666.1297685  0.456
2008 Bhardwaj S, Vrudhula S, Goel A. A unified approach for full chip statistical timing and leakage analysis of nanoscale circuits considering intradie process variations Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 1812-1825. DOI: 10.1109/Tcad.2008.927671  0.365
2008 Bhardwaj S, Vrudhula S. Leakage minimization of digital circuits using gate sizing in the presence of process variations Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 445-455. DOI: 10.1109/Tcad.2008.916341  0.381
2007 Rao R, Vrudhula S. Energy optimal speed control of a producer--consumer device pair Acm Transactions in Embedded Computing Systems. 6: 30. DOI: 10.1145/1274858.1274868  0.413
2007 Ghanta P, Vrudhula S. Analysis of power supply noise in the presence of process variations Ieee Design and Test of Computers. 24: 256-266. DOI: 10.1109/Mdt.2007.61  0.357
2006 Rao R, Vrudhula S, Chakrabarti C, Chang N. An optimal analytical solution for processor speed control with thermal constraints Proceedings of the International Symposium On Low Power Electronics and Design. 2006: 292-297. DOI: 10.1145/1165573.1165643  0.303
2006 Cho Y, Chang N, Chakrabarti C, Vrudhula S. High-level power management of embedded systems with application-specific energy cost functions Proceedings - Design Automation Conference. 568-573. DOI: 10.1145/1146909.1147057  0.309
2006 Zhuo J, Chakrabarti C, Chang N, Vrudhula S. Extending the lifetime of fuel cell based hybrid systems Proceedings - Design Automation Conference. 562-567. DOI: 10.1145/1146909.1147056  0.312
2006 Shu T, Krunz M, Vrudhula S. Joint optimization of transmit power-time and bit energy efficiency in CDMA wireless sensor networks Ieee Transactions On Wireless Communications. 5: 3109-3118. DOI: 10.1109/Twc.2006.04738  0.438
2006 Rao R, Vrudhula S. Energy-optimal speed control of a generic device Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 2737-2746. DOI: 10.1109/Tcad.2006.882598  0.43
2006 Vrudhula S, Wang JM, Ghanta P. Hermite polynomial based interconnect analysis in the presence of process variations Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 2001-2010. DOI: 10.1109/Tcad.2005.862734  0.372
2006 Bhardwaj S, Vrudhula S, Cao Y. LOTUS: Leakage optimization under timing uncertainty for standard-cell designs Proceedings - International Symposium On Quality Electronic Design, Isqed. 717-722. DOI: 10.1109/ISQED.2006.83  0.327
2005 Bhardwaj S, Vrudhula S, Blaauw D. Probability distribution of signal arrival times using Bayesian networks Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 24: 1784-1794. DOI: 10.1109/Tcad.2005.852436  0.329
2005 Rao R, Vrudhula S. Energy optimal speed control of devices with discrete speed sets Proceedings - Design Automation Conference. 901-904.  0.322
2004 Rao R, Vrudhula S, Krishnan MS. Disk drive energy optimization for audio-video applications Cases 2004: International Conference On Compilers, Architecture, and Synthesis For Embedded Systems. 93-103.  0.329
2004 Sreeramaneni R, Vrudhula SBK. Energy profiler for hardware/software Co-design Proceedings of the Ieee International Conference On Vlsi Design. 17: 335-340.  0.412
2003 Rakhmatov D, Vrudhula S. Energy management for battery-powered embedded systems Acm Transactions in Embedded Computing Systems. 2: 277-324. DOI: 10.1145/860176.860179  0.753
2003 Rakhmatov D, Vrudhula S, Wallach DA. A model for battery lifetime analysis for organizing applications on a pocket computer Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 11: 1019-1030. DOI: 10.1109/Tvlsi.2003.819320  0.734
2003 Rao R, Vrudhula S, Rakhmatov DN. Battery Modeling for Energy-Aware System Design Computer. 36. DOI: 10.1109/Mc.2003.1250886  0.737
2003 Rao R, Vrudhula S, Rakhmatov D. Analysis of Discharge Techniques for Multiple Battery Systems Proceedings of the International Symposium On Low Power Electronics and Design. 44-47.  0.304
2002 Rakhmatov DN, Vrudhula SBK. Hardware-software bipartitioning for dynamically reconfigurable systems Hardware/Software Codesign - Proceedings of the International Workshop. 145-150.  0.723
2002 Rakhmatov D, Vrudhula S, Chakrabarti C. Battery-conscious task sequencing for portable devices including voltage/clock scaling Proceedings - Design Automation Conference. 189-194.  0.326
2002 Rakhmatov D, Vrudhula S, Wallach DA. Battery lifetime prediction for energy-aware computing Proceedings of the International Symposium On Low Power Electronics and Design, Digest of Technical Papers. 154-159.  0.422
2001 Rakhmatov DN, Vrudhula SBK. An analytical high-level battery model for use in energy management of portable electronic systems Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 488-493.  0.745
2001 Rakhmatov D, Vrudhula SBK. Time-to-failure estimation for batteries in portable electronic systems Proceedings of the International Symposium On Low Power Electronics and Design, Digest of Technical Papers. 88-91.  0.35
2000 Rakhmatov DN, Vrudhula SBK, Brown TJ, Nagarandal A. Adaptive multiuser online reconfigurable engine Ieee Design and Test of Computers. 17: 53-67. DOI: 10.1109/54.825677  0.692
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