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Ronald Dreslinski, Ph.D. - Publications

Affiliations: 
2011 University of Michigan, Ann Arbor, Ann Arbor, MI 
Area:
Computer Engineering, Computer Science, Electronics and Electrical Engineering
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48 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Park D, Pal S, Feng S, Gao P, Tan J, Rovinski A, Xie S, Zhao C, Amarnath A, Wesley T, Beaumont J, Chen K, Chakrabarti C, Taylor MB, Mudge T, ... ... Dreslinski RG, et al. A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix–Matrix Multiplication Accelerator Ieee Journal of Solid-State Circuits. 55: 933-944. DOI: 10.1109/Jssc.2019.2960480  0.688
2018 Davidson S, Xie S, Torng C, Al-Hawai K, Rovinski A, Ajayi T, Vega L, Zhao C, Zhao R, Dai S, Amarnath A, Veluri B, Gao P, Rao A, Liu G, ... ... Dreslinski R, et al. The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips Ieee Micro. 38: 30-41. DOI: 10.1109/Mm.2018.022071133  0.439
2018 Li Z, Dong Q, Saligane M, Kempke B, Gong L, Zhang Z, Dreslinski R, Sylvester D, Blaauw D, Kim H. A 1920 $\times $ 1080 30-frames/s 2.3 TOPS/W Stereo-Depth Processor for Energy-Efficient Autonomous Navigation of Micro Aerial Vehicles Ieee Journal of Solid-State Circuits. 53: 76-90. DOI: 10.1109/Jssc.2017.2751501  0.489
2017 Pinckney N, Jeloka S, Dreslinski R, Mudge T, Sylvester D, Blaauw D, Shifren L, Cline B, Sinha S. Impact of FinFET on Near-Threshold Voltage Scalability Ieee Design & Test. 34: 31-38. DOI: 10.1109/Mdat.2016.2630303  0.644
2016 Hauswald J, Laurenzano MA, Zhang Y, Yang H, Kang Y, Li C, Rovinski A, Khurana A, Dreslinski RG, Mudge T, Petrucci V, Tang L, Mars J. Designing future warehouse-scale computers for sirius, an end-to-end voice and vision personal assistant Acm Transactions On Computer Systems. 34. DOI: 10.1145/2870631  0.58
2016 Lukefahr A, Padmanabha S, Das R, Sleiman FM, Dreslinski RG, Wenisch TF, Mahlke S. Exploring fine-grained heterogeneity with composite cores Ieee Transactions On Computers. 65: 535-547. DOI: 10.1109/Tc.2015.2419669  0.342
2016 Pannuto P, Lee Y, Kuo YS, Foo ZY, Kempke B, Kim G, Dreslinski RG, Blaauw D, Dutta P. MBus: A System Integration Bus for the Modular Microscale Computing Class Ieee Micro. 36: 60-70. DOI: 10.1109/Mm.2016.41  0.33
2016 Hauswald J, Laurenzano MA, Zhang Y, Li C, Rovinski A, Khurana A, Dreslinski RG, Mudge T, Petrucci V, Tang L, Mars J. Sirius Implications for Future Warehouse-Scale Computers Ieee Micro. 36: 42-53. DOI: 10.1109/Mm.2016.37  0.533
2016 Chen Y, Chiotellis N, Chuo L, Pfeiffer C, Shi Y, Dreslinski RG, Grbic A, Mudge T, Wentzloff DD, Blaauw D, Kim HS. Energy-Autonomous Wireless Communication for Millimeter-Scale Internet-of-Things Sensor Nodes Ieee Journal On Selected Areas in Communications. 34: 3962-3977. DOI: 10.1109/Jsac.2016.2612041  0.55
2016 Chen Y, Lu S, Kim HS, Blaauw D, Dreslinski RG, Mudge T. A low power software-defined-radio baseband processor for the Internet of Things Proceedings - International Symposium On High-Performance Computer Architecture. 2016: 40-51. DOI: 10.1109/HPCA.2016.7446052  0.615
2016 Dreslinski RG, Fick D, Giridhar B, Kim G, Seo S, Fojtik M, Satpathy S, Lee Y, Kim D, Liu N, Wieckowski M, Chen G, Mudge T, Sylvester D, Blaauw D. Centip3De: A 64-core, 3D stacked, near-threshold system 2012 Ieee Hot Chips 24 Symposium, Hcs 2012. DOI: 10.1109/HOTCHIPS.2012.7476490  0.353
2015 Pannuto P, Lee Y, Kuo YS, Foo Z, Kempke B, Kim G, Dreslinski RG, Blaauw D, Dutta P. MBus: An Ultra-Low Power Interconnect Bus for Next Generation Nanopower Systems. Proceedings / Annual International Symposium On Computer Architecture. International Symposium On Computer Architecture. 2015: 629-641. PMID 26855555 DOI: 10.1145/2749469.2750376  0.332
2015 Kloosterman J, Beaumont J, Wollman M, Sethia A, Dreslinski R, Mudge T, Mahlke S. WarpPool: Sharing requests with inter-warp coalescing for throughput processors Proceedings of the Annual International Symposium On Microarchitecture, Micro. 5: 433-444. DOI: 10.1145/2830772.2830830  0.304
2015 Gao C, Gutierrez A, Rajan M, Dreslinski RG, Mudge T, Wu CJ. A study of mobile device utilization Ispass 2015 - Ieee International Symposium On Performance Analysis of Systems and Software. 225-234. DOI: 10.1109/ISPASS.2015.7095808  0.362
2014 Lukefahr A, Padmanabha S, Das R, Dreslinski R, Wenisch TF, Mahlke S. Heterogeneous microarchitectures trump voltage scaling for low-power cores Parallel Architectures and Compilation Techniques - Conference Proceedings, Pact. 237-249. DOI: 10.1145/2628071.2628078  0.4
2014 Gutierrez A, Cieslak M, Giridhar B, Dreslinski RG, Ceze L, Mudge T. Integrated 3D-stacked server designs for increasing physical density of key-value stores International Conference On Architectural Support For Programming Languages and Operating Systems - Asplos. 485-498. DOI: 10.1145/2541940.2541951  0.358
2014 Gutierrez A, Dreslinski RG, Mudge T. Evaluating private vs. shared last-level caches for energy efficiency in asymmetric multi-cores Proceedings - International Conference On Embedded Computer Systems: Architectures, Modeling and Simulation, Samos 2014. 191-198. DOI: 10.1109/SAMOS.2014.6893211  0.6
2014 Gao C, Gutierrez A, Dreslinski RG, Mudge T, Flautner K, Blake G. A study of Thread Level Parallelism on mobile devices Ispass 2014 - Ieee International Symposium On Performance Analysis of Systems and Software. 126-127. DOI: 10.1109/ISPASS.2014.6844468  0.665
2014 Hauswald J, Manville T, Zheng Q, Dreslinski R, Chakrabarti C, Mudge T. A hybrid approach to offloading mobile image classification Icassp, Ieee International Conference On Acoustics, Speech and Signal Processing - Proceedings. 8375-8379. DOI: 10.1109/ICASSP.2014.6855235  0.55
2014 Zheng Q, Chen Y, Lee H, Dreslinski R, Chakrabarti C, Anastasopoulos A, Mahlke S, Mudge T. Using Graphics Processing Units in an LTE Base Station Journal of Signal Processing Systems. 78: 35-47. DOI: 10.1007/s11265-014-0932-x  0.307
2013 Dreslinski RG, Fick D, Giridhar B, Kim G, Seo S, Fojtik M, Satpathy S, Lee Y, Kim D, Liu N, Wieckowski M, Chen G, Sylvester D, Blaauw D, Mudge T. Centip3De: A many-core prototype exploring 3d integration and near-threshold computing Communications of the Acm. 56: 97-104. DOI: 10.1145/2524713.2524725  0.694
2013 Giridhar B, Cieslak M, Duggal D, Dreslinski R, Chen HM, Patti R, Hold B, Chakrabarti C, Mudge T, Blaauw D. Exploring DRAM organizations for energy-efficient and resilient exascale memories International Conference For High Performance Computing, Networking, Storage and Analysis, Sc. DOI: 10.1145/2503210.2503215  0.332
2013 Pinckney N, Dreslinski RG, Sewell K, Fick D, Mudge T, Sylvester D, Blaauw D. Limits of parallelism and boosting in dim silicon Ieee Micro. 33: 30-37. DOI: 10.1109/Mm.2013.73  0.741
2013 Dreslinski RG, Fick D, Giridhar B, Kim G, Seo S, Fojtik M, Satpathy S, Lee Y, Kim D, Liu N, Wieckowski M, Chen G, Sylvester D, Blaauw D, Mudge T. Centip3De: A 64-Core, 3D stacked near-threshold system Ieee Micro. 33: 8-16. DOI: 10.1109/Mm.2013.4  0.702
2013 Fick D, Dreslinski RG, Giridhar B, Kim G, Seo S, Fojtik M, Satpathy S, Lee Y, Kim D, Liu N, Wieckowski M, Chen G, Mudge T, Blaauw D, Sylvester D. Centip3De: A cluster-based NTC architecture with 64 ARM cortex-M3 cores in 3D stacked 130 nm CMOS Ieee Journal of Solid-State Circuits. 48: 104-117. DOI: 10.1109/Jssc.2012.2222814  0.688
2013 Tandon P, Qazvinian V, Chang J, Ranganathan P, Dreslinski RG, Wenisch TF. Hardware acceleration for similarity measurement in natural language processing Proceedings of the International Symposium On Low Power Electronics and Design. 409-414. DOI: 10.1109/ISLPED.2013.6629333  0.372
2013 Zheng Q, Chen Y, Dreslinski R, Chakrabarti C, Anastasopoulos A, Mahlke S, Mudge T. Architecting an LTE base station with graphics processing units Ieee Workshop On Signal Processing Systems, Sips: Design and Implementation. 219-224.  0.323
2012 Gutierrez A, Pusdesris J, Dreslinski RG, Mudge T. Lazy cache invalidation for self-modifying codes Cases'12 - Proceedings of the 2012 Acm International Conference On Compilers, Architectures and Synthesis For Embedded Systems, Co-Located With Esweek. 151-160. DOI: 10.1145/2380403.2380433  0.539
2012 Seo S, Dreslinski RG, Woh M, Park Y, Charkrabari C, Mahlke S, Blaauw D, Mudge T. Process variation in near-threshold wide SIMD architectures Proceedings - Design Automation Conference. 980-987. DOI: 10.1145/2228360.2228536  0.765
2012 Lukefahr A, Padmanabha S, Das R, Sleiman FM, Dreslinski R, Wenisch TF, Mahlke S. Composite cores: Pushing heterogeneity into a core Proceedings - 2012 Ieee/Acm 45th International Symposium On Microarchitecture, Micro 2012. 317-328. DOI: 10.1109/MICRO.2012.37  0.392
2012 Sewell K, Dreslinski RG, Manville T, Satpathy S, Pinckney N, Blake G, Cieslak M, Das R, Wenisch TF, Sylvester D, Blaauw D, Mudge T. Swizzle-switch networks for many-core systems Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 2: 278-294. DOI: 10.1109/Jetcas.2012.2193936  0.744
2012 Sleiman FM, Dreslinski RG, Wenisch TF. Embedded way prediction for last-level caches Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 167-174. DOI: 10.1109/ICCD.2012.6378636  0.349
2011 Blake G, Dreslinski RG, Mudge T. Bloom filter guided transaction scheduling Proceedings - International Symposium On High-Performance Computer Architecture. 75-86. DOI: 10.1109/HPCA.2011.5749718  0.435
2011 Woh M, Satpathy S, Dreslinski RG, Kershaw D, Sylvester D, Blaauw D, Mudge T. Low power interconnects for SIMD computers Proceedings -Design, Automation and Test in Europe, Date. 600-605.  0.735
2011 Satpathy S, Dreslinski R, Ou TC, Sylvester D, Mudge T, Blaauw D. SWIFT: A 2.1Tb/s 32x32 self-arbitrating manycore interconnect fabric Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 138-139.  0.451
2010 Seo S, Dreslinski RG, Who M, Chakrabarti C, Mahlke S, Mudge T. Diet SODA: A power-efficient processor for digital cameras Proceedings of the International Symposium On Low Power Electronics and Design. 79-84. DOI: 10.1145/1840845.1840862  0.345
2010 Blake G, Dreslinski RG, Mudge T, Flautner K. Evolution of thread-level parallelism in desktop applications Proceedings - International Symposium On Computer Architecture. 302-313. DOI: 10.1145/1815961.1816000  0.732
2010 Wieckowski M, Dreslinski RG, Mudge T, Blaauw D, Sylvester D. Circuit design advances for ultra-low power sensing platforms Proceedings of Spie - the International Society For Optical Engineering. 7679. DOI: 10.1117/12.850720  0.61
2010 Dreslinski RG, Wieckowski M, Blaauw D, Sylvester D, Mudge T. Near-threshold computing: Reclaiming moore's law through energy efficient integrated circuits Proceedings of the Ieee. 98: 253-266. DOI: 10.1109/JPROC.2009.2034764  0.396
2009 Blake G, Dreslinski RG, Mudge T. Proactive transaction scheduling for contention management Proceedings of the Annual International Symposium On Microarchitecture, Micro. 156-167. DOI: 10.1145/1669112.1669133  0.556
2009 Blake G, Dreslinski RG, Mudge T. A survey of multicore processors: A review of their common attributes Ieee Signal Processing Magazine. 26: 26-37. DOI: 10.1109/Msp.2009.934110  0.596
2009 Dreslinski RG, Fick D, Blaauw D, Sylvester D, Mudge T. Reconfigurable multicore server processors for low power operation Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 5657: 247-254. DOI: 10.1007/978-3-642-03138-0_27  0.375
2008 Dreslinski RG, Chen GK, Mudge T, Blaauw D, Sylvester D, Flautner K. Reconfigurable energy efficient near threshold cache architectures Proceedings of the Annual International Symposium On Microarchitecture, Micro. 459-470. DOI: 10.1109/MICRO.2008.4771813  0.716
2008 Özer E, Dreslinski RG, Mudge T, Biles S, Flautner K. Energy-efficient simultaneous thread fetch from different cache levels in a soft real-time SMT processor Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 5114: 12-22. DOI: 10.1007/978-3-540-70550-5_3  0.734
2007 Zhai B, Dreslinski RG, Blaauw D, Mudge T, Sylvester D. Energy efficient near-threshold chip multi-processing Proceedings of the International Symposium On Low Power Electronics and Design. 32-37. DOI: 10.1145/1283780.1283789  0.406
2007 Dreslinski RG, Saidi AG, Mudge T, Reinhardt SK. Analysis of hardware prefetching across virtual page boundaries 2007 Computing Frontiers, Conference Proceedings. 13-22. DOI: 10.1145/1242531.1242537  0.461
2007 Dreslinski RG, Zhai B, Mudge T, Blaauw D, Sylvester D. An energy efficient parallel architecture using near threshold operation Parallel Architectures and Compilation Techniques - Conference Proceedings, Pact. 175-185. DOI: 10.1109/PACT.2007.41  0.395
2006 Kgil T, D'Souza S, Saidi A, Binkert N, Dreslinski R, Mudge T, Reinhardt S, Flautner K. PicoServer: Using 3D stacking technology to enable a compact energy efficient chip multiprocessor International Conference On Architectural Support For Programming Languages and Operating Systems - Asplos. 117-128. DOI: 10.1145/1168857.1168873  0.67
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