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Siddharth Garg, Ph.D. - Publications

Affiliations: 
2009 Carnegie Mellon University, Pittsburgh, PA 
Area:
Electronics and Electrical Engineering
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21 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Zhang J, Ghodsi Z, Garg S, Rangineni K. Enabling Timing Error Resilience for Low-Power Systolic-Array Based Deep Learning Accelerators Ieee Design & Test of Computers. 37: 93-102. DOI: 10.1109/Mdat.2019.2947271  0.395
2020 Collantes MIM, Garg S. Do Not Trust, Verify: A Verifiable Hardware Accelerator for Matrix Multiplication Ieee Embedded Systems Letters. 12: 70-73. DOI: 10.1109/Les.2019.2953485  0.341
2019 Zhang J(, Raj P, Zarar S, Ambardekar A, Garg S. CompAct: On-chip Com pression of Act ivations for Low Power Systolic Array Based CNN Acceleration Acm Transactions in Embedded Computing Systems. 18: 47. DOI: 10.1145/3358178  0.349
2019 Cui X, Zhang J(, Wu K, Garg S, Karri R. Split Manufacturing-Based Register Transfer-Level Obfuscation Acm Journal On Emerging Technologies in Computing Systems. 15: 1-22. DOI: 10.1145/3289156  0.357
2019 Pilato C, Wu K, Garg S, Karri R, Regazzoni F. TaintHLS: High-Level Synthesis for Dynamic Information Flow Tracking Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 38: 798-808. DOI: 10.1109/Tcad.2018.2834421  0.354
2018 Pilato C, Garg S, Wu K, Karri R, Regazzoni F. Securing Hardware Accelerators: A New Challenge for High-Level Synthesis Ieee Embedded Systems Letters. 10: 77-80. DOI: 10.1109/Les.2017.2774800  0.32
2017 Turakhia Y, Liu G, Garg S, Marculescu D. Thread Progress Equalization: Dynamically Adaptive Power-Constrained Performance Optimization of Multi-Threaded Applications Ieee Transactions On Computers. 66: 731-744. DOI: 10.1109/Tc.2016.2608951  0.721
2017 Shafique M, Garg S, Chandra V. Guest Editors’ Introduction: Computing in the Dark Silicon Era Ieee Design & Test of Computers. 34: 5-7. DOI: 10.1109/Mdat.2017.2651065  0.434
2017 Shafique M, Garg S. Computing in the Dark Silicon Era: Current Trends and Research Challenges Ieee Design & Test of Computers. 34: 8-23. DOI: 10.1109/Mdat.2016.2633408  0.33
2016 Cai E, Juan DC, Garg S, Park J, Marculescu D. Learning-Based Power/Performance Optimization for Many-Core Systems with Extended-Range Voltage/Frequency Scaling Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 35: 1318-1331. DOI: 10.1109/Tcad.2015.2504330  0.731
2016 Kriebel F, Shafique M, Rehman S, Henkel J, Garg S. Variability and Reliability Awareness in the Age of Dark Silicon Ieee Design and Test. 33: 59-67. DOI: 10.1109/Mdat.2015.2439640  0.409
2014 Juan DC, Garg S, Marculescu D. Statistical peak temperature prediction and thermal yield improvement for 3D chip multiprocessors Acm Transactions On Design Automation of Electronic Systems. 19. DOI: 10.1145/2633606  0.713
2013 Garg S, Marculescu D. Mitigating the impact of process variation on the performance of 3-D integrated circuits Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 21: 1903-1914. DOI: 10.1109/Tvlsi.2012.2226762  0.691
2013 Xia J, Garg S, Boumaiza S. A Hybrid Amplitude/Time Encoding Scheme for Enhancing Coding Efficiency and Dynamic Range in Digitally Modulated Power Amplifiers Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 3: 498-507. DOI: 10.1109/Jetcas.2013.2284616  0.379
2012 Garg S, Marculescu D, Marculescu R. Technology-driven limits on runtime power management algorithms for multiprocessor systems-on-chip Acm Journal On Emerging Technologies in Computing Systems. 8. DOI: 10.1145/2367736.2367739  0.75
2012 Garg S, Marculescu D. On the impact of manufacturing process variations on the lifetime of sensor networks Transactions On Embedded Computing Systems. 11. DOI: 10.1145/2220336.2220345  0.645
2012 Garg S, Marculescu D. System-level leakage variability mitigation for MPSoC platforms using body-bias islands Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 20: 2289-2301. DOI: 10.1109/Tvlsi.2011.2171512  0.716
2012 Herbert S, Garg S, Marculescu D. Exploiting process variability in voltage/frequency control Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 20: 1392-1404. DOI: 10.1109/Tvlsi.2011.2160001  0.733
2012 Rajendiran A, Ananthanarayanan S, Patel HD, Tripunitara MV, Garg S. Reliable computing with ultra-reduced instruction set co-processors Proceedings - Design Automation Conference. 697-702. DOI: 10.1109/Mm.2013.130  0.324
2008 Garg S, Marculescu D. System-level throughput analysis for process variation aware multiple voltage-frequency island designs Acm Transactions On Design Automation of Electronic Systems. 13. DOI: 10.1145/1391962.1391967  0.71
2008 Marculescu D, Garg S. Process-driven variability analysis of single and multiple voltage-frequency island latency-constrained systems Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 893-904. DOI: 10.1109/Tcad.2008.917969  0.687
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