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Francis G. Wolff, Ph.D. - Publications

Affiliations: 
2001 Case Western Reserve University, Cleveland Heights, OH, United States 
Area:
Computer Science, Electronics and Electrical Engineering
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13 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2015 Al-Khaleel O, Al-Qudah Z, Al-Khaleel M, Bani-Hani R, Papachristou CA, Wolff FG. Efficient Hardware Implementations of Binary-to-BCD Conversion Schemes for Decimal Multiplication Journal of Circuits, Systems, and Computers. 24: 1550019. DOI: 10.1142/S021812661550019X  0.583
2013 Narasimhan S, Du D, Chakraborty RS, Paul S, Wolff FG, Papachristou CA, Roy K, Bhunia S. Hardware trojan detection by multiple-parameter side-channel analysis Ieee Transactions On Computers. 62: 2183-2195. DOI: 10.1109/Tc.2012.200  0.655
2012 Leinweber L, Papachristou C, Wolff FG. An efficient elliptic curve cryptography processor using addition chains with high information entropy 2012 25th Ieee Canadian Conference On Electrical and Computer Engineering: Vision For a Greener Future, Ccece 2012. DOI: 10.1109/CCECE.2012.6334841  0.339
2011 Al-Omari H, Papachristou C, Wolff F, Mcintyre D. Smoothing delay jitter in networked control systems Journal of Embedded Computing. 4: 11-21. DOI: 10.3233/Jec-2009-0103  0.602
2011 Al-Khaleel O, Al-Khaleel M, Al-Qudahj Z, Papachristou CA, Mhaidat K, Wolff FG. Fast binary/decimal adder/subtractor with a novel correction-free BCD addition 2011 18th Ieee International Conference On Electronics, Circuits, and Systems, Icecs 2011. 455-459. DOI: 10.1109/ICECS.2011.6122311  0.673
2011 Al-Khaleel O, Al-Qudah Z, Al-Khaleel M, Papachristou CA, Wolff FG. Fast and compact binary-to-BCD conversion circuits for decimal multiplication Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 226-231. DOI: 10.1109/ICCD.2011.6081401  0.672
2009 Leinweber L, Papachristou C, Wolff FG. Efficient architectures for elliptic curve cryptography processors for RFID Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 372-377. DOI: 10.1109/ICCD.2009.5413128  0.397
2007 Gill BS, Papachristou C, Wolff FG. A new asymmetric SRAM cell to reduce soft errors and leakage power in FPGA Proceedings -Design, Automation and Test in Europe, Date. 1460-1465. DOI: 10.1109/DATE.2007.364504  0.494
2006 Gill BS, Papachristou C, Wolff FG. Soft delay error analysis in logic circuits Proceedings -Design, Automation and Test in Europe, Date. 1.  0.555
2005 Gill BS, Papachristou C, Wolff FG, Seifert N. Node sensitivity analysis for soft errors in CMOS logic Proceedings - International Test Conference. 2005: 964-972. DOI: 10.1109/TEST.2005.1584062  0.347
2004 Gill BS, Papachristou C, Wolff FG. Soft delay error effects in CMOS combinational circuits Proceedings of the Ieee Vlsi Test Symposium. 325-330. DOI: 10.1109/VTEST.2004.1299260  0.569
2004 Wolff FG, Papachristou C, McIntyre DR. Test compression and hardware decompression for scan-based SoCs Proceedings - Design, Automation and Test in Europe Conference and Exhibition. 1: 716-717. DOI: 10.1109/DATE.2004.1268945  0.302
2003 Knieser MJ, Wolff FG, Papachristou CA, Weyer DJ, McIntyre DR. A technique for high ratio LZW compression Proceedings -Design, Automation and Test in Europe, Date. 116-121. DOI: 10.1109/DATE.2003.1253596  0.552
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