| Year |
Citation |
Score |
| 2016 |
Gent K, Hsiao MS. A control path aware metric for grading functional test vectors Lats 2016 - 17th Ieee Latin-American Test Symposium. 51-56. DOI: 10.1109/LATW.2016.7483339 |
0.421 |
|
| 2015 |
Gent K, Hsiao MS. Abstraction-based relation mining for functional test generation Proceedings of the Ieee Vlsi Test Symposium. 2015. DOI: 10.1109/VTS.2015.7116286 |
0.312 |
|
| 2015 |
Prabhu S, Acharya VV, Bagri S, Hsiao MS. A diagnosis-friendly LBIST architecture with property checking Proceedings - International Test Conference. 2015. DOI: 10.1109/TEST.2014.7035359 |
0.386 |
|
| 2015 |
Acharya VV, Bagri S, Hsiao MS. Branch guided functional test generation at the RTL Proceedings - 2015 20th Ieee European Test Symposium, Ets 2014. DOI: 10.1109/ETS.2015.7138737 |
0.324 |
|
| 2014 |
Bhunia S, Hsiao MS, Banga M, Narasimhan S. Hardware trojan attacks: Threat analysis and countermeasures Proceedings of the Ieee. 102: 1229-1247. DOI: 10.1109/JPROC.2014.2334493 |
0.683 |
|
| 2014 |
Liao KY, Chen PJ, Lin AF, Li JCM, Hsiao MS, Wang LT. GPU-based timing-aware test generation for small delay defects Proceedings - 2014 19th Ieee European Test Symposium, Ets 2014. DOI: 10.1109/ETS.2014.6847835 |
0.326 |
|
| 2014 |
Gent K, Hsiao MS. Dual-purpose mixed-level test generation using swarm intelligence Proceedings of the Asian Test Symposium. 230-235. DOI: 10.1109/ATS.2014.50 |
0.365 |
|
| 2013 |
Bhunia S, Abramovici M, Agrawal D, Hsiao MS, Plusquellic J, Tehranipoor M, Bradley P. Protection against hardware trojan attacks: Towards a comprehensive solution Ieee Design and Test. 30: 6-17. DOI: 10.1109/Mdt.2012.2196252 |
0.349 |
|
| 2012 |
Wu S, Wang L, Wen X, Jone W, Hsiao MS, Li F, Li JC, Huang J. Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains Acm Transactions On Design Automation of Electronic Systems. 17: 48. DOI: 10.1145/2348839.2348852 |
0.361 |
|
| 2012 |
Prabhu S, Hsiao MS, Lingappan L, Gangaram V. A SMT-based diagnostic test generation method for combinational circuits Proceedings of the Ieee Vlsi Test Symposium. 215-220. DOI: 10.1109/VTS.2012.6231105 |
0.435 |
|
| 2012 |
Shrestha G, Hsiao MS. Ensuring trust of third-party hardware design with constrained sequential equivalence checking 2012 Ieee International Conference On Technologies For Homeland Security, Hst 2012. 7-12. DOI: 10.1109/THS.2012.6459818 |
0.315 |
|
| 2012 |
Li M, Gent K, Hsiao MS. Design validation of RTL circuits using evolutionary swarm intelligence Proceedings - International Test Conference. DOI: 10.1109/TEST.2012.6401556 |
0.316 |
|
| 2012 |
Nguyen H, Hsiao MS. Sequential equivalence checking of hard instances with targeted inductive invariants and efficient filtering strategies Proceedings - Ieee International High-Level Design Validation and Test Workshop, Hldvt. 1-8. DOI: 10.1109/HLDVT.2012.6418236 |
0.305 |
|
| 2012 |
Li M, Hsiao MS. RAG: An efficient reliability analysis of logic circuits on graphics processing units Proceedings -Design, Automation and Test in Europe, Date. 316-319. |
0.316 |
|
| 2011 |
Chandrasekar M, Hsiao MS. Fault collapsing using a novel extensibility relation Proceedings of the Ieee International Conference On Vlsi Design. 268-273. DOI: 10.1109/VLSID.2011.56 |
0.404 |
|
| 2011 |
Li M, Hsiao MS. 3-D parallel fault simulation with GPGPU Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 30: 1545-1555. DOI: 10.1109/TCAD.2011.2158432 |
0.32 |
|
| 2011 |
Banga M, Hsiao MS. ODETTE: A non-scan design-for-test methodology for Trojan detection in ICs 2011 Ieee International Symposium On Hardware-Oriented Security and Trust, Host 2011. 18-23. DOI: 10.1109/HST.2011.5954989 |
0.746 |
|
| 2011 |
Li M, Hsiao MS. High-performance diagnostic fault simulation on GPUs Proceedings - 16th Ieee European Test Symposium, Ets 2011. 210. DOI: 10.1109/ETS.2011.41 |
0.365 |
|
| 2011 |
Krishnamoorthy S, Hsiao MS, Lingappan L. Strategies for scalable symbolic execution-driven test generation for programs Science China Information Sciences. 54: 1797-1812. DOI: 10.1007/S11432-011-4368-7 |
0.321 |
|
| 2011 |
Banga M, Rahagude N, Hsiao MS. Design-for-test methodology for non-scan at-speed testing Proceedings -Design, Automation and Test in Europe, Date. 191-196. |
0.775 |
|
| 2010 |
Wu S, Wang L, Wen X, Jiang Z, Tan L, Zhang Y, Hu Y, Jone W, Hsiao MS, Li JC, Huang J, Yu L. Using Launch-on-Capture for Testing BIST Designs Containing Synchronous and Asynchronous Clock Domains Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 29: 299-312. DOI: 10.1109/Tcad.2009.2035483 |
0.411 |
|
| 2010 |
Banga M, Hsiao MS. Trusted RTL: Trojan detection methodology in pre-silicon designs Proceedings of the 2010 Ieee International Symposium On Hardware-Oriented Security and Trust, Host 2010. 56-59. DOI: 10.1109/HST.2010.5513114 |
0.715 |
|
| 2010 |
Goel N, Hsiao MS, Ramakrishnan N, Zaki MJ. Mining complex boolean expressions for sequential equivalence checking Proceedings of the Asian Test Symposium. 442-447. DOI: 10.1109/ATS.2010.81 |
0.342 |
|
| 2010 |
Rahagude N, Chandrasekar M, Hsiao MS. DFT + DFD: An integrated method for design for testability and diagnosability Proceedings of the Asian Test Symposium. 218-223. DOI: 10.1109/ATS.2010.46 |
0.426 |
|
| 2010 |
Li M, Hsiao MS. FSimGP2: An efficient fault simulator with GPGPU Proceedings of the Asian Test Symposium. 15-20. DOI: 10.1109/ATS.2010.12 |
0.334 |
|
| 2010 |
Chandrasekar M, Rahagude NP, Hsiao MS. Search state compatibility based incremental learning framework and output deviation based X-filling for diagnostic test generation Journal of Electronic Testing: Theory and Applications (Jetta). 26: 165-176. DOI: 10.1007/S10836-010-5142-2 |
0.509 |
|
| 2009 |
Banga M, Hsiao MS. A novel sustained vector technique for the detection of hardware trojans Proceedings: 22nd International Conference On Vlsi Design - Held Jointly With 7th International Conference On Embedded Systems. 327-332. DOI: 10.1109/VLSI.Design.2009.22 |
0.743 |
|
| 2009 |
Donglikar S, Banga M, Chandrasekar M, Hsiao MS. Fast circuit topology based method to configure the scan chains in Illinois scan architecture Proceedings - International Test Conference. DOI: 10.1109/TEST.2009.5355661 |
0.747 |
|
| 2009 |
Banga M, Hsiao MS. VITAMIN: Voltage inversion technique to ascertain malicious insertions in ICs 2009 Ieee International Workshop On Hardware-Oriented Security and Trust, Host 2009. 104-107. DOI: 10.1109/HST.2009.5224960 |
0.729 |
|
| 2009 |
Chandrasekar M, Hsiao MS. Diagnostic test generation for Silicon Diagnosis with an incremental learning framework based on search state compatibility Proceedings - Ieee International High-Level Design Validation and Test Workshop, Hldvt. 68-75. DOI: 10.1109/HLDVT.2009.5340172 |
0.422 |
|
| 2009 |
Hsiao MS, Banga M. Kiss the scan goodbye: A non-scan architecture for high coverage, low test data volume and low test application time Proceedings of the Asian Test Symposium. 225-230. DOI: 10.1109/ATS.2009.17 |
0.737 |
|
| 2009 |
Li JCM, Hsiao MS. Fault Simulation and Test Generation Electronic Design Automation. 851-917. DOI: 10.1016/B978-0-12-374364-0.50021-7 |
0.382 |
|
| 2008 |
Fang L, Hsiao MS. Boosting SAT Solver Performance via a New Hybrid Approach Journal On Satisfiability, Boolean Modeling and Computation. 5: 243-261. DOI: 10.3233/Sat190058 |
0.325 |
|
| 2008 |
He N, Hsiao MS. A new testability guided abstraction to solving bit-vector formula Acm International Conference Proceeding Series. 39-45. DOI: 10.1145/1512464.1512473 |
0.537 |
|
| 2008 |
Banga M, Chandrasekar M, Lei F, Hsiao MS. Guided test generation for isolation and detection of embedded trojans in ICs Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 363-366. DOI: 10.1145/1366110.1366196 |
0.74 |
|
| 2008 |
Li B, Fang L, Hsiao MS. Efficient power droop aware delay fault testing Proceedings - International Test Conference. DOI: 10.1109/TEST.2007.4437597 |
0.394 |
|
| 2008 |
Wu W, Hsiao MS. Mining global constraints with domain knowledge for improving bounded sequential equivalence checking Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 197-201. DOI: 10.1109/Tcad.2007.907240 |
0.363 |
|
| 2008 |
Banga M, Hsiao MS. A region based approach for the identification of hardware Trojans 2008 Ieee International Workshop On Hardware-Oriented Security and Trust, Host. 40-47. DOI: 10.1109/HST.2008.4559047 |
0.743 |
|
| 2008 |
Hank Walker DM, Hsiao MS. Delay Testing System-On-Chip Test Architectures. 263-306. DOI: 10.1016/B978-012373973-5.50011-5 |
0.369 |
|
| 2008 |
Kim HS, Kang S, Hsiao MS. A new scan architecture for both low power testing and test volume compression under SOC test environment Journal of Electronic Testing: Theory and Applications (Jetta). 24: 365-378. DOI: 10.1007/S10836-008-5062-6 |
0.379 |
|
| 2008 |
Fang L, Hsiao MS. Bilateral testing of nano-scale fault-tolerant circuits Journal of Electronic Testing: Theory and Applications (Jetta). 24: 285-296. DOI: 10.1007/S10836-007-5041-3 |
0.505 |
|
| 2007 |
Vimjam VC, Hsiao MS. Explicit safety property strengthening in SAT-based induction Proceedings of the Ieee International Conference On Vlsi Design. 63-68. DOI: 10.1109/VLSID.2007.80 |
0.76 |
|
| 2007 |
Chen X, Hsiao MS. An overlapping scan architecture for reducing both test time and test power by pipelining fault detection Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 15: 404-412. DOI: 10.1109/Tvlsi.2007.893657 |
0.477 |
|
| 2007 |
Syal M, Chandrasekar K, Vimjam V, Hsiao MS, Chang YS, Chakravarty S. A study of implication based pseudo functional testing Proceedings - International Test Conference. DOI: 10.1109/TEST.2006.297667 |
0.699 |
|
| 2007 |
Wu W, Hsiao MS. Mining sequential constraints for pseudo-functional testing Proceedings of the Asian Test Symposium. 19-24. DOI: 10.1109/ATS.2007.4387977 |
0.411 |
|
| 2006 |
Wu W, Hsiao MS. Mining global constraints for improving bounded sequential equivalence checking Proceedings - Design Automation Conference. 743-748. DOI: 10.1145/1146909.1147098 |
0.304 |
|
| 2006 |
Vimjam VC, Hsiao MS. Fast illegal state identification for improving SAT-based induction Proceedings - Design Automation Conference. 241-246. DOI: 10.1145/1146909.1146972 |
0.779 |
|
| 2006 |
Vimjam VC, Hsiao MS. Efficient fault collapsing via generalized dominance relations Proceedings of the Ieee Vlsi Test Symposium. 2006: 258-263. DOI: 10.1109/VTS.2006.31 |
0.786 |
|
| 2006 |
Zhang L, Ghosh I, Hsiao MS. A framework for automatic design validation of RTL circuits using ATPG and observability-enhanced tag coverage Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 2526-2537. DOI: 10.1109/Tcad.2006.881333 |
0.388 |
|
| 2006 |
Wu Q, Hsiao MS. State variable extraction and partitioning to reduce problem complexity for ATPG and design validation Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 2263-2268. DOI: 10.1109/Tcad.2005.859512 |
0.413 |
|
| 2006 |
Syal M, Hsiao MS. New techniques for untestable fault identification in sequential circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 1117-1131. DOI: 10.1109/Tcad.2005.855967 |
0.746 |
|
| 2006 |
Chen X, Hsiao MS. Testing embedded sequential cores in parallel using spectrum-based BIST Ieee Transactions On Computers. 55: 150-162. DOI: 10.1109/Tc.2006.30 |
0.407 |
|
| 2006 |
Lei F, Hsiao MS. Bilateral testing of nano-scale fault-tolerant circuits Proceedings - Ieee International Symposium On Defect and Fault Tolerance in Vlsi Systems. 309-317. DOI: 10.1109/DFT.2006.17 |
0.417 |
|
| 2006 |
Hsiao MS. Test generation Vlsi Test Principles and Architectures. 161-262. DOI: 10.1016/B978-012370597-6/50008-1 |
0.395 |
|
| 2005 |
Liu X, Hsiao MS, Chakravarty S, Thadikaran PJ. Efficient techniques for transition testing Acm Transactions On Design Automation of Electronic Systems. 10: 258-278. DOI: 10.1145/1059876.1059880 |
0.393 |
|
| 2005 |
Liu X, Hsiao MS. A novel transition fault ATPG that reduces yield loss Ieee Design and Test of Computers. 22: 576-584. DOI: 10.1109/Mdt.2005.126 |
0.461 |
|
| 2005 |
Syal M, Arora R, Hsiao MS. Extended forward implications and dual recurrence relations to identify sequentially untestable faults Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 2005: 453-460. DOI: 10.1109/ICCD.2005.53 |
0.735 |
|
| 2005 |
Vimjam VC, Hsiao MS. Increasing the deductibility in CNF instances for efficient SAT-based bounded model checking Proceedings - Ieee International High-Level Design Validation and Test Workshop, Hldvt. 2005: 184-191. DOI: 10.1109/HLDVT.2005.1568835 |
0.776 |
|
| 2005 |
Syal M, Hsiao MS. VERISEC: VERIfying equivalence of sequential circuits using SAT Proceedings - Ieee International High-Level Design Validation and Test Workshop, Hldvt. 2005: 52-59. DOI: 10.1109/HLDVT.2005.1568813 |
0.687 |
|
| 2005 |
Chandrasekar K, Hsiao MS. Integration of learning techniques into incremental satisfiability for efficient path-delay fault test generation Proceedings -Design, Automation and Test in Europe, Date '05. 1002-1007. DOI: 10.1109/DATE.2005.187 |
0.409 |
|
| 2005 |
Syal M, Natarajan S, Chakravarty S, Hsiao MS. Untestable multi-cycle path delay faults in industrial designs Proceedings of the Asian Test Symposium. 2005: 194-201. DOI: 10.1109/ATS.2005.111 |
0.703 |
|
| 2005 |
Vimjam VC, Syal M, Hsiao MS. Untestable fault identification through enhanced necessary value assignments Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 176-181. |
0.778 |
|
| 2004 |
Sheng S, Hsiao MS. Success-driven learning in ATPG for preimage computation Ieee Design and Test of Computers. 21: 504-512. DOI: 10.1109/Mdt.2004.97 |
0.317 |
|
| 2004 |
Liu X, Hsiao MS. On identifying functionally untestable transition faults Proceedings - Ieee International High-Level Design Validation and Test Workshop, Hldvt. 121-126. DOI: 10.1109/HLDVT.2004.1431252 |
0.36 |
|
| 2004 |
Gupta P, Hsiao MS. ALAPTF: A new transition fault model and the ATPG algorithm Proceedings - International Test Conference. 1053-1060. |
0.34 |
|
| 2004 |
Arora R, Hsiao MS. Using global structural relationships of signals to accelerate SAT-based combinational equivalence checking Journal of Universal Computer Science. 10: 1597-1628. |
0.328 |
|
| 2004 |
Syal M, Chakravarty S, Hsiao MS. Identifying untestable transition faults in latch based designs with multiple clocks Proceedings - International Test Conference. 1034-1043. |
0.68 |
|
| 2004 |
Syal M, Hsiao MS. Untestable fault identification using recurrence relations and impossible value assignments Proceedings of the Ieee International Conference On Vlsi Design. 17: 481-486. |
0.728 |
|
| 2004 |
Arora R, Hsiao MS. Enhancing SAT-based bounded model checking using sequential logic implications Proceedings of the Ieee International Conference On Vlsi Design. 17: 784-787. |
0.352 |
|
| 2003 |
Syal M, Hsiao MS, Doreswamy KB, Chakravarty S. Efficient implication-based untestable bridge fault identifier Proceedings of the Ieee Vlsi Test Symposium. 2003: 393-398. DOI: 10.1109/VTEST.2003.1197680 |
0.721 |
|
| 2003 |
Chen X, Hsiao MS. Energy-efficient logic BIST based on state correlation analysis Proceedings of the Ieee Vlsi Test Symposium. 2003: 267-272. DOI: 10.1109/VTEST.2003.1197662 |
0.355 |
|
| 2003 |
Liu X, Hsiao MS. Constrained ATPG for broadside transition testing Proceedings - Ieee International Symposium On Defect and Fault Tolerance in Vlsi Systems. 2003: 175-182. DOI: 10.1109/TSM.2005.1250110 |
0.348 |
|
| 2003 |
Syal M, Hsiao MS. A novel, low-cost algorithm for sequentially untestable fault identification Proceedings -Design, Automation and Test in Europe, Date. 316-321. DOI: 10.1109/DATE.2003.1253626 |
0.716 |
|
| 2003 |
Liu X, Hsiao MS, Chakravarty S, Thadikaran PJ. Efficient transition fault ATPG algorithms based on stuck-at test vectors Journal of Electronic Testing: Theory and Applications (Jetta). 19: 437-445. DOI: 10.1023/A:1024696110831 |
0.452 |
|
| 2003 |
Wu Q, Hsiao MS. Efficient Sequential ATPG Based on Partitioned Finite-State-Machine Traversal Ieee International Test Conference (Tc). 281-289. |
0.346 |
|
| 2003 |
Gupta P, Hsiao MS. High Quality ATPG for Delay Defects Ieee International Test Conference (Tc). 584-591. |
0.377 |
|
| 2002 |
Chen X, Hsiao MS. Characteristic faults and spectral information for logic BIST Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 294-298. DOI: 10.1145/774572.774616 |
0.396 |
|
| 2002 |
Sheng S, Hsiao MS. Efficient sequential test generation based on logic simulation Ieee Design and Test of Computers. 19: 56-64. DOI: 10.1109/Mdt.2002.1033793 |
0.471 |
|
| 2002 |
Liu X, Hsiao MS, Chakravarty S, Thadikaran PJ. Novel ATPG algorithms for transition faults Proceedings of the European Test Workshop. 2002: 47-52. DOI: 10.1109/ETW.2002.1029638 |
0.347 |
|
| 2002 |
Hsiao MS. Maximizing impossibilities for untestable fault identification Proceedings -Design, Automation and Test in Europe, Date. 949-953. DOI: 10.1109/DATE.2002.998414 |
0.428 |
|
| 2002 |
Hsiao MS. Genetic spot optimization for peak power estimation in large VLSI circuits Vlsi Design. 15: 407-416. DOI: 10.1080/1065514021000012020 |
0.372 |
|
| 2002 |
Giani A, Sheng S, Hsiao MS, Agrawal VD. State and fault information for compaction-based test generation Journal of Electronic Testing: Theory and Applications (Jetta). 18: 63-72. DOI: 10.1023/A:1013780023643 |
0.524 |
|
| 2002 |
Sheng S, Takayama K, Hsiao MS. Effective safety property checking using simulation-based sequential ATPG Proceedings - Design Automation Conference. 813-818. |
0.301 |
|
| 2001 |
Giani A, Sheng S, Hsiao MS, Agrawal VD. Efficient spectral techniques for sequential ATPG Proceedings -Design, Automation and Test in Europe, Date. 204-208. DOI: 10.1109/DATE.2001.915025 |
0.344 |
|
| 2001 |
D'Souza AL, Hsiao MS. Error diagnosis of sequential circuits using region-based model Proceedings of the Ieee International Conference On Vlsi Design. 103-108. DOI: 10.1007/S10836-005-6141-6 |
0.34 |
|
| 2001 |
Giani A, Sheng S, Hsiao MS, Agrawal VD. Novel spectral methods for built-in self-test in a system-on-a-chip environment Proceedings of the Ieee Vlsi Test Symposium. 163-168. |
0.312 |
|
| 2000 |
Hsiao MS, Rudnick EM, Patel JH. Dynamic state traversal for sequential circuit test generation Acm Transactions On Design Automation of Electronic Systems. 5: 548-565. DOI: 10.1145/348019.348288 |
0.461 |
|
| 2000 |
Hsiao MS, Rudnick EM, Patel JH. Peak power estimation of VLSI circuits: New peak power measures Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 8: 435-439. DOI: 10.1109/92.863624 |
0.331 |
|
| 2000 |
Hsiao MS, Chakradhar S. Test set compaction using relaxed subsequence removal Journal of Electronic Testing: Theory and Applications (Jetta). 16: 319-327. DOI: 10.1023/A:1008361817867 |
0.465 |
|
| 2000 |
Hsiao MS, Chakradhar S. Test set and fault partitioning techniques for static test sequence compaction for sequential circuits Journal of Electronic Testing: Theory and Applications (Jetta). 16: 329-338. DOI: 10.1023/A:1008313901938 |
0.489 |
|
| 1999 |
Hsiao MS, Rudnick EM, Patel JH. Fast static compaction algorithms for sequential circuit test vectors Ieee Transactions On Computers. 48: 311-322. DOI: 10.1109/12.754997 |
0.473 |
|
| 1999 |
Hsiao MS. On non-statistical techniques for fast fault coverage estimation Journal of Electronic Testing: Theory and Applications (Jetta). 15: 239-254. DOI: 10.1023/A:1008332723359 |
0.469 |
|
| 1998 |
Hsiao MS, Chakradhary ST. State relaxation based subsequence removal for fast static compaction in sequential circuits Proceedings -Design, Automation and Test in Europe, Date. 577-582. DOI: 10.1109/DATE.1998.655916 |
0.391 |
|
| 1998 |
Hsiao MS, Rudnick EM, Patel JH. Application of genetically engineered finite-statemachine sequences to sequential circuit ATPG Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 17: 239-254. DOI: 10.1109/43.700722 |
0.459 |
|
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