| Year |
Citation |
Score |
| 2020 |
Venkataramani V, Kulkarni A, Mitra T, Peh L. SPECTRUM Acm Transactions On Embedded Computing Systems. 19: 1-28. DOI: 10.1145/3400032 |
0.406 |
|
| 2017 |
Jerger NE, Krishna T, Peh L. On-Chip Networks, Second Edition Synthesis Lectures On Computer Architecture. 12: 1-210. DOI: 10.2200/S00772ED1V01Y201704CAC040 |
0.384 |
|
| 2017 |
Tan C, Kulkarni A, Venkataramani V, Karunaratne M, Mitra T, Peh L. LOCUS: Low-Power Customizable Many-Core Architecture for Wearables Acm Transactions in Embedded Computing Systems. 17: 16. DOI: 10.1145/3122786 |
0.488 |
|
| 2017 |
Choi P, Radhakrishna U, Boon CC, Peh L, Antoniadis D. Linearity Enhancement of a Fully Integrated 6-GHz GaN Power Amplifier Ieee Microwave and Wireless Components Letters. 27: 927-929. DOI: 10.1109/Lmwc.2017.2746673 |
0.43 |
|
| 2016 |
Daya BK, Peh LS, Chandrakasan AP. Quest for high-performance bufferless NoCs with single-cycle express paths and self-learning throttling Proceedings - Design Automation Conference. 5. DOI: 10.1145/2897937.2898075 |
0.459 |
|
| 2016 |
Choi P, Radhakrishna U, Boon CC, Antoniadis D, Peh LS. A Fully Integrated Inductor-Based GaN Boost Converter with Self-Generated Switching Signal for Vehicular Applications Ieee Transactions On Power Electronics. 31: 5365-5368. DOI: 10.1109/Tpel.2016.2518183 |
0.378 |
|
| 2016 |
Daya BK, Peh LS, Chandrakasan AP. Towards high-performance bufferless NoCs with SCEPTER Ieee Computer Architecture Letters. 15: 62-65. DOI: 10.1109/Lca.2015.2428699 |
0.567 |
|
| 2015 |
Choi P, Gao J, Ramanathan N, Mao M, Xu S, Boon CC, Fahmy SA, Peh LS. A case for leveraging 802.11p for direct phone-to-phone communications Proceedings of the International Symposium On Low Power Electronics and Design. 2015: 207-212. DOI: 10.1145/2627369.2627644 |
0.302 |
|
| 2015 |
Choi P, Goswami S, Radhakrishna U, Khanna D, Boon CC, Lee HS, Antoniadis D, Peh LS. A 5.9-GHz fully integrated GaN frontend design with physics-based RF compact model Ieee Transactions On Microwave Theory and Techniques. 63: 1163-1173. DOI: 10.1109/Tmtt.2015.2405913 |
0.448 |
|
| 2015 |
Krishna T, Peh LS. Single-cycle collective communication over a shared network fabric Proceedings - 2014 8th Ieee/Acm International Symposium On Networks-On-Chip, Nocs 2014. 1-8. DOI: 10.1109/NOCS.2014.7008755 |
0.43 |
|
| 2014 |
Hetu SN, Hamishagi VS, Peh LS. Similitude: Interfacing a traffic simulator and network simulator with emulated android clients Ieee Vehicular Technology Conference. DOI: 10.1109/VTCFall.2014.6966178 |
0.314 |
|
| 2014 |
Choi P, Goswami S, Boon CC, Peh LS, Lee HS. A fully integrated 5.9GHz RF frontend in 0.25um GaN-on-SiC for vehicle-to-vehicle applications Digest of Papers - Ieee Radio Frequency Integrated Circuits Symposium. 397-400. DOI: 10.1109/RFIC.2014.6851751 |
0.368 |
|
| 2014 |
Krishna T, Chen CHO, Kwon WC, Peh LS. Smart: Single-cycle multihop traversals over a shared network on chip Ieee Micro. 34: 43-56. DOI: 10.1109/Mm.2014.48 |
0.574 |
|
| 2014 |
Wang H, Peh LS. Mobistreams: A reliable distributed stream processing system for mobile devices Proceedings of the International Parallel and Distributed Processing Symposium, Ipdps. 51-60. DOI: 10.1109/IPDPS.2014.17 |
0.39 |
|
| 2014 |
Sankaran K, Ananda AL, Chan MC, Peh LS. Dynamic framework for building highly-localized mobile web DTN applications Chants 2014 - Proceedings of the 9th Acm Mobicom Workshop On Challenged Networks. 43-48. DOI: 10.1016/J.Comcom.2015.08.017 |
0.331 |
|
| 2013 |
Postman J, Krishna T, Edmonds C, Peh LS, Chiang P. SWIFT: A low-power network-on-chip implementing the token flow control router architecture with swing-reduced interconnects Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 21: 1432-1446. DOI: 10.1109/Tvlsi.2012.2211904 |
0.718 |
|
| 2013 |
Krishna T, Chen CO, Park S, Kwon W, Subramanian S, Chandrakasan AP, Peh L. Single-Cycle Multihop Asynchronous Repeated Traversal: A SMART Future for Reconfigurable On-Chip Networks Computer. 46: 48-55. DOI: 10.1109/Mc.2013.260 |
0.501 |
|
| 2013 |
Krishna T, Chen CHO, Kwon WC, Peh LS. Breaking the on-chip latency barrier using SMART Proceedings - International Symposium On High-Performance Computer Architecture. 378-389. DOI: 10.1109/HPCA.2013.6522334 |
0.48 |
|
| 2013 |
Park S, Qazi M, Peh LS, Chandrakasan AP. 40.4fJ/bit/mm low-swing on-chip signaling with self-resetting logic repeaters embedded within a mesh NoC in 45nm SOI CMOS Proceedings -Design, Automation and Test in Europe, Date. 1637-1642. |
0.342 |
|
| 2012 |
Li B, Peh LS, Zhao L, Iyer R. Dynamic QoS management for chip multiprocessors Transactions On Architecture and Code Optimization. 9. DOI: 10.1145/2355585.2355590 |
0.392 |
|
| 2012 |
Kahng AB, Li B, Peh LS, Samadi K. Orion 2.0: A power-area simulator for interconnection networks Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 20: 191-196. DOI: 10.1109/Tvlsi.2010.2091686 |
0.519 |
|
| 2012 |
Koukoumidis E, Martonosi M, Peh LS. Leveraging smartphone cameras for collaborative road advisories Ieee Transactions On Mobile Computing. 11: 707-723. DOI: 10.1109/Tmc.2011.275 |
0.325 |
|
| 2012 |
Gao J, Sivaraman A, Agarwal N, Li H, Peh LS. DIPLOMA: Consistent and coherent shared memory over mobile phones Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 371-378. DOI: 10.1109/ICCD.2012.6378666 |
0.337 |
|
| 2011 |
Ramanujam RS, Soteriou V, Lin B, Peh LS. Extending the effective throughput of NoCs with distributed shared-buffer routers Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 30: 548-561. DOI: 10.1109/Tcad.2011.2110550 |
0.583 |
|
| 2011 |
Aisopos K, DeOrio A, Peh LS, Bertacco V. Ariadne: Agnostic reconfiguration in a disconnected network environment Parallel Architectures and Compilation Techniques - Conference Proceedings, Pact. 298-309. DOI: 10.1109/PACT.2011.61 |
0.354 |
|
| 2011 |
Chen CHO, Park S, Krishna T, Peh LS. A low-swing crossbar and link generator for low-power networks-on-chip Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 779-786. DOI: 10.1109/ICCAD.2011.6105418 |
0.494 |
|
| 2011 |
DeOrio A, Aisopos K, Bertacco V, Peh LS. DRAIN: Distributed Recovery Architecture for Inaccessible Nodes in multi-core chips Proceedings - Design Automation Conference. 912-917. |
0.306 |
|
| 2010 |
Hari P, McCabe JBP, Banafato J, Henry M, Ko K, Koukoumidis E, Kremer U, Martonosi M, Peh LS. Adaptive spatiotemporal node selection in dynamic networks Parallel Architectures and Compilation Techniques - Conference Proceedings, Pact. 227-236. DOI: 10.1145/1854273.1854304 |
0.334 |
|
| 2010 |
Ramanujam RS, Soteriou V, Lin B, Peh LS. Design of a high-throughput distributed shared-buffer NoC router Nocs 2010 - the 4th Acm/Ieee International Symposium On Networks-On-Chip. 69-78. DOI: 10.1109/NOCS.2010.17 |
0.518 |
|
| 2010 |
Krishna T, Postman J, Edmonds C, Peh LS, Chiang P. SWIFT: A swing-reduced interconnect for a Token-based Network-On-Chip in 90nm CMOS Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 439-446. DOI: 10.1109/ICCD.2010.5647666 |
0.706 |
|
| 2009 |
Jerger NE, Peh LS. On-Chip networks Synthesis Lectures On Computer Architecture. 8: 1-137. DOI: 10.2200/S00209ED1V01Y200907CAC008 |
0.504 |
|
| 2009 |
Agarwal N, Peh LS, Jha NK. In-network coherence filtering: Snoopy coherence without broadcasts Proceedings of the Annual International Symposium On Microarchitecture, Micro. 232-243. DOI: 10.1145/1669112.1669143 |
0.421 |
|
| 2009 |
Kolodny A, Peh LS. Special section on international symposium on networks-on-chip (NOCS) Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 17: 317-318. DOI: 10.1109/Tvlsi.2009.2012524 |
0.541 |
|
| 2009 |
Marculescu R, Ogras UY, Peh LS, Jerger NE, Hoskote Y. Outstanding research problems in NoC design: System, microarchitecture, and circuit perspectives Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 28: 3-21. DOI: 10.1109/Tcad.2008.2010691 |
0.395 |
|
| 2009 |
Krishna T, Kumar A, Peh LS, Postman J, Chiang P, Erez M. Express virtual channels with capacitively driven global links Ieee Micro. 29: 48-61. DOI: 10.1109/Mm.2009.64 |
0.709 |
|
| 2009 |
Krishna T, Kumar A, Postman J, Chiang P, Erez M, Peh L. NOCHI: Network-on-Chip with Hybrid Interconnect Ieee Micro. 1-1. DOI: 10.1109/Mm.2009.53 |
0.748 |
|
| 2009 |
Soteriou V, Ramanujam RS, Lin B, Peh LS. A high-throughput distributed shared-buffer NoC router Ieee Computer Architecture Letters. 8: 21-24. DOI: 10.1109/L-Ca.2009.5 |
0.571 |
|
| 2009 |
Agarwal N, Krishna T, Peh LS, Jha NK. GARNET: A detailed on-chip network model inside a full-system simulator Ispass 2009 - International Symposium On Performance Analysis of Systems and Software. 33-42. DOI: 10.1109/ISPASS.2009.4919636 |
0.53 |
|
| 2009 |
Agarwal N, Peh LS, Jha NK. In-Network Snoop Ordering (INSO): Snoopy coherence on unordered interconnects Proceedings - International Symposium On High-Performance Computer Architecture. 67-78. DOI: 10.1109/HPCA.2009.4798238 |
0.391 |
|
| 2009 |
Kahng AB, Bin L, Peh LS, Samadi K. ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration Proceedings -Design, Automation and Test in Europe, Date. 423-428. |
0.367 |
|
| 2008 |
Eisley N, Peh LS, Shang L. Leveraging on-chip networks for data cache migration in chip multiprocessors Parallel Architectures and Compilation Techniques - Conference Proceedings, Pact. 197-207. DOI: 10.1145/1454115.1454144 |
0.402 |
|
| 2008 |
Chen X, Wei GY, Peh LS. Design of low-power short-distance opto-electronic transceiver front-ends with scalable supply voltages and frequencies Proceedings of the International Symposium On Low Power Electronics and Design. 277-282. DOI: 10.1145/1393921.1393994 |
0.341 |
|
| 2008 |
Kumar A, Shang L, Peh LS, Jha NK. System-level dynamic thermal management for high-performance microprocessors Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 96-107. DOI: 10.1109/Tcad.2007.907062 |
0.347 |
|
| 2008 |
Kumar A, Peh LS, Kundu P, Jha NK. Toward ideal on-chip communication using express virtual channels Ieee Micro. 28: 80-90. DOI: 10.1109/Mm.2008.18 |
0.533 |
|
| 2008 |
Kumar A, Peh LS, Jha NK. Token flow control Proceedings of the Annual International Symposium On Microarchitecture, Micro. 342-353. DOI: 10.1109/MICRO.2008.4771803 |
0.498 |
|
| 2008 |
Jerger NDE, Peh LS, Lipasti MH. Virtual tree coherence: Leveraging regions and in-network multicast trees for scalable cache coherence Proceedings of the Annual International Symposium On Microarchitecture, Micro. 35-46. DOI: 10.1109/MICRO.2008.4771777 |
0.353 |
|
| 2008 |
Yeh D, Peh L, Borkar S, Darringer J, Agarwal A, Hwu W. Thousand-Core Chips [Roundtable] Ieee Design & Test of Computers. 25: 272-278. DOI: 10.1109/Mdt.2008.85 |
0.356 |
|
| 2008 |
Hoskote Y, Marculescu R, Peh LS. Guest editors' introduction: Tackling key problems in NoCs Ieee Design and Test of Computers. 25: 400-401. DOI: 10.1109/Mdt.2008.141 |
0.417 |
|
| 2008 |
Jerger NE, Peh LS, Lipasti M. Virtual circuit tree multicasting: A case for on-chip hardware multicast support Proceedings - International Symposium On Computer Architecture. 229-240. DOI: 10.1109/ISCA.2008.12 |
0.494 |
|
| 2008 |
Kumar A, Agarwal N, Peh LS, Jha NK. A system-level perspective for efficient NoC design Ipdps Miami 2008 - Proceedings of the 22nd Ieee International Parallel and Distributed Processing Symposium, Program and Cd-Rom. DOI: 10.1109/IPDPS.2008.4536409 |
0.473 |
|
| 2008 |
Krishna T, Kumar A, Chiang P, Erez M, Peh LS. NoC with near-ideal express virtual channels using global-line communication Proceedings - Symposium On the High Performance Interconnects, Hot Interconnects. 11-20. DOI: 10.1109/HOTI.2008.22 |
0.734 |
|
| 2007 |
Wang Y, Martonosi M, Peh L. Predicting link quality using supervised learning in wireless sensor networks Mobile Computing and Communications Review. 11: 71-83. DOI: 10.1145/1317425.1317434 |
0.336 |
|
| 2007 |
Kumar A, Peh LS, Kundu P, Jha NK. Express virtual channels: Towards the ideal interconnection fabric Proceedings - International Symposium On Computer Architecture. 150-161. DOI: 10.1145/1250662.1250681 |
0.531 |
|
| 2007 |
Soteriou V, Eisley N, Wang H, Li B, Peh LS. Polaris: A system-level roadmapping toolchain for on-chip interconnection networks Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 15: 855-868. DOI: 10.1109/Tvlsi.2007.900725 |
0.549 |
|
| 2007 |
Luo J, Jha NK, Peh L. Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems Ieee Transactions On Very Large Scale Integration Systems. 15: 427-437. DOI: 10.1109/Tvlsi.2007.893660 |
0.476 |
|
| 2007 |
Soteriou V, Peh LS. Exploring the design space of self-regulating power-aware on/off interconnection networks Ieee Transactions On Parallel and Distributed Systems. 18: 393-408. DOI: 10.1109/TPDS.2007.43 |
0.485 |
|
| 2007 |
Owens JD, Dally WJ, Ho R, Jayashima DN, Keckler SW, Peh LS. Research challenges for on-chip interconnection networks Ieee Micro. 27: 96-108. DOI: 10.1109/Mm.2007.91 |
0.651 |
|
| 2007 |
Kundu P, Peh LS. Guest editors' introduction: On-chip interconnects for multicores Ieee Micro. 27: 3-5. DOI: 10.1109/Mm.2007.85 |
0.515 |
|
| 2007 |
Jerger NE, Lipasti M, Peh LS. Circuit-switched coherence Ieee Computer Architecture Letters. 6. DOI: 10.1109/L-Ca.2007.2 |
0.456 |
|
| 2007 |
Kumar A, Kundu P, Singh AP, Peh LS, Jha NK. A 4.6Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS 2007 Ieee International Conference On Computer Design, Iccd 2007. 63-70. DOI: 10.1109/ICCD.2007.4601881 |
0.51 |
|
| 2006 |
Eisley N, Soteriou V, Peh LS. High-level power analysis for multi-core chips Cases 2006: International Conference On Compilers, Architecture and Synthesis For Embedded Systems. 389-400. DOI: 10.1145/1176760.1176807 |
0.485 |
|
| 2006 |
Wang Y, Want CY, Martonosi M, Peh LS. Transport layer approaches for improving idle energy in challenged sensor networks Proceedings of Acm Sigcomm 2006 - Conference On Applications, Technologies, Architectures, and Protocols For Computer Communication. 2006: 253-260. DOI: 10.1145/1162654.1162663 |
0.361 |
|
| 2006 |
Shang L, Peh LS, Jha NK. PowerHerd: A distributed scheme for dynamically satisfying peak-power constraints in interconnection networks Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 92-110. DOI: 10.1109/Tcad.2005.852438 |
0.543 |
|
| 2006 |
Li S, Peh LS, Kumar A, Jha NK. Temperature-aware on-chip networks Ieee Micro. 26: 130-139. DOI: 10.1109/Mm.2006.23 |
0.411 |
|
| 2006 |
Eisley N, Peh LS, Shang L. In-network cache coherence Ieee Computer Architecture Letters. 5: 34-37. DOI: 10.1109/L-Ca.2006.9 |
0.463 |
|
| 2006 |
Soteriou V, Eisley N, Wang H, Li B, Peh LS. Polaris: A system-level roadmap for on-chip interconnection networks Ieee International Conference On Computer Design, Iccd 2006. 134-141. DOI: 10.1109/ICCD.2006.4380806 |
0.496 |
|
| 2006 |
Wang Y, Martonosi M, Peh LS. Situation-aware caching strategies in highly varying mobile networks Proceedings - Ieee Computer Society's Annual International Symposium On Modeling, Analysis, and Simulation of Computer and Telecommunications Systems, Mascots. 265-274. |
0.346 |
|
| 2006 |
Soteriou V, Wang H, Peh LS. A statistical traffic model for on-chip interconnection networks Proceedings - Ieee Computer Society's Annual International Symposium On Modeling, Analysis, and Simulation of Computer and Telecommunications Systems, Mascots. 104-116. |
0.453 |
|
| 2005 |
Soteriou V, Eisley N, Peh LS. Software-directed power-aware interconnection networks Cases 2005: International Conference On Compilers, Architecture, and Synthesis For Embedded Systems. 274-285. DOI: 10.1145/1216544.1216548 |
0.598 |
|
| 2005 |
Chen J, Juang P, Ko K, Contreras G, Penry D, Rangan R, Stoler A, Peh L, Martonosi M. Hardware-modulated parallelism in chip multiprocessors Acm Sigarch Computer Architecture News. 33: 54-63. DOI: 10.1145/1105734.1105742 |
0.442 |
|
| 2005 |
Peh LS, Pinkston TM. Guest editorial: Special section on on-chip networks Ieee Transactions On Parallel and Distributed Systems. 16: 97-98. DOI: 10.1109/TPDS.2005.19 |
0.332 |
|
| 2005 |
Chen X, Peh LS, Wei GY, Huang YK, Prucnal P. Exploring the design space of power-aware opto-electronic networked systems Proceedings - International Symposium On High-Performance Computer Architecture. 120-131. DOI: 10.1109/HPCA.2005.15 |
0.441 |
|
| 2005 |
Wang H, Peh LS, Malik S. A technology-aware and energy-oriented topology exploration for on-chip networks Proceedings -Design, Automation and Test in Europe, Date '05. 1238-1243. DOI: 10.1109/DATE.2005.40 |
0.489 |
|
| 2005 |
August DI, Malik S, Peh LS, Pai V, Vachharajani M, Willmann P. Achieving structural and composable modeling of complex systems International Journal of Parallel Programming. 33: 81-101. DOI: 10.1007/S10766-005-3569-3 |
0.301 |
|
| 2005 |
Juang P, Wu Q, Peh LS, Martonosi M, Clark DW. Coordinated, distributed, formal energy management of chip multiprocessors Proceedings of the International Symposium On Low Power Electronics and Design. 127-130. |
0.351 |
|
| 2004 |
Wang Y, Martonosi M, Peh L. MARio Acm Sigmobile Mobile Computing and Communications Review. 8: 77-81. DOI: 10.1145/1052871.1052881 |
0.457 |
|
| 2004 |
Eisley N, Peh LS. High-level power analysis for on-chip networks Cases 2004: International Conference On Compilers, Architecture, and Synthesis For Embedded Systems. 104-115. |
0.511 |
|
| 2004 |
Soteriou V, Peh LS. Design-space exploration of power-aware on/off interconnection networks Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 510-517. |
0.469 |
|
| 2004 |
Shang L, Peh LS, Kumar A, Jha NK. Thermal modeling, characterization and management of on-chip networks Proceedings of the Annual International Symposium On Microarchitecture, Micro. 67-78. |
0.369 |
|
| 2003 |
Wang HS, Peh LS, Malik S. A power model for routers: Modeling alpha 21364 and InfiniBand routers Ieee Micro. 23: 26-35. DOI: 10.1109/Mm.2003.1179895 |
0.528 |
|
| 2003 |
Wang H, Peh LS, Malik S. Power-driven design of router microarchitectures in on-chip networks Proceedings of the Annual International Symposium On Microarchitecture, Micro. 2003: 105-116. DOI: 10.1109/MICRO.2003.1253187 |
0.517 |
|
| 2003 |
Shang L, Peh LS, Jha NK. Dynamic voltage scaling with links for power optimization of interconnection networks Proceedings - International Symposium On High-Performance Computer Architecture. 12: 91-102. DOI: 10.1109/HPCA.2003.1183527 |
0.495 |
|
| 2003 |
Luo J, Peh LS, Jha N. Simultaneous dynamic voltage scaling of processors and communication links in real-time distributed embedded systems Proceedings -Design, Automation and Test in Europe, Date. 1150-1151. DOI: 10.1109/DATE.2003.1253776 |
0.358 |
|
| 2003 |
Soteriou V, Peh LS. Dynamic power management for power optimization of interconnection networks using on/off links Proceedings - 11th Symposium On High Performance Interconnects, Hoti 2003. 15-20. DOI: 10.1109/CONECT.2003.1231472 |
0.471 |
|
| 2003 |
Chen X, Peh LS. Leakage Power Modeling and Optimization in Interconnection Networks Proceedings of the International Symposium On Low Power Electronics and Design. 90-95. |
0.421 |
|
| 2003 |
Shang L, Peh LS, Jha NK. Power Herd: Dynamic Satisfaction of Peak Power Constraints in Interconnection Networks Proceedings of the International Conference On Supercomputing. 98-108. |
0.456 |
|
| 2002 |
Philo J, Hidekazu O, Yong W, Margaret M, Peh LS, Rubenstein D. Energy-efficient computing for wildlife tracking: Design tradeoffs and early experiences with ZebraNet Operating Systems Review (Acm). 36: 96-107. DOI: 10.1145/635508.605408 |
0.344 |
|
| 2002 |
Wang HS, Zhu X, Peh LS, Malik S. Orion: A power-performance simulator for interconnection networks Proceedings of the Annual International Symposium On Microarchitecture, Micro. 2002: 294-305. DOI: 10.1109/MICRO.2002.1176258 |
0.441 |
|
| 2002 |
Shang L, Peh L, Jha NK. Power-efficient Interconnection Networks: Dynamic Voltage Scaling with Links Ieee Computer Architecture Letters. 1: 6-6. DOI: 10.1109/L-Ca.2002.10 |
0.43 |
|
| 2002 |
Juang P, Oki H, Wang Y, Martonosi M, Peh LS, Rubenstein D. Energy-efficient computing for wildlife tracking: Design tradeoffs and early experiences with ZebraNet International Conference On Architectural Support For Programming Languages and Operating Systems - Asplos. 96-107. |
0.344 |
|
| 2001 |
Peh LS, Dally WJ, Li-Shiuan P. Delay model for router microarchitectures Ieee Micro. 21: 26-34. DOI: 10.1109/40.903059 |
0.364 |
|
| 2000 |
Peh LS, Dally WJ. Flit-reservation flow control Ieee High-Performance Computer Architecture Symposium Proceedings. 73-84. |
0.309 |
|
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