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Jae-sun Seo, Ph.D. - Publications

Affiliations: 
2010 University of Michigan, Ann Arbor, Ann Arbor, MI 
Area:
Electronics and Electrical Engineering
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40 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Cherupally SK, Yin S, Kadetotad D, Srivastava G, Bae C, Kim SJ, Seo JS. ECG Authentication Neural Network Hardware Design with Collective Optimization of Low Precision and Structured Compression. Ieee Transactions On Biomedical Circuits and Systems. PMID 32078561 DOI: 10.1109/Tbcas.2020.2974387  0.39
2020 Yin S, Jiang Z, Kim M, Gupta T, Seok M, Seo J. Vesti: Energy-Efficient In-Memory Computing Accelerator for Deep Neural Networks Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 28: 48-61. DOI: 10.1109/Tvlsi.2019.2940649  0.442
2020 Yin S, Sun X, Yu S, Seo J. High-Throughput In-Memory Computing for Binary Deep Neural Networks with Monolithically Integrated RRAM and 90nm CMOS. Ieee Transactions On Electron Devices. 1-8. DOI: 10.1109/Ted.2020.3015178  0.341
2020 Shim W, Luo Y, Seo J, Yu S. Investigation of Read Disturb and Bipolar Read Scheme on Multilevel RRAM-Based Deep Learning Inference Engine Ieee Transactions On Electron Devices. 67: 2318-2323. DOI: 10.1109/Ted.2020.2985013  0.339
2020 Ma Y, Cao Y, Vrudhula S, Seo J. Performance Modeling for CNN Inference Accelerators on FPGA Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 39: 843-856. DOI: 10.1109/Tcad.2019.2897634  0.41
2020 Ma Y, Cao Y, Vrudhula S, Seo J. Automatic Compilation of Diverse CNNs Onto High-Performance FPGA Accelerators Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 39: 424-437. DOI: 10.1109/Tcad.2018.2884972  0.382
2020 Kadetotad D, Yin S, Berisha V, Chakrabarti C, Seo J. An 8.93 TOPS/W LSTM Recurrent Neural Network Accelerator Featuring Hierarchical Coarse-Grain Sparsity for On-Device Speech Recognition Ieee Journal of Solid-State Circuits. 55: 1877-1887. DOI: 10.1109/Jssc.2020.2992900  0.417
2020 Jiang Z, Yin S, Seo J, Seok M. C3SRAM: An In-Memory-Computing SRAM Macro Based on Robust Capacitive Coupling Computing Mechanism Ieee Journal of Solid-State Circuits. 55: 1888-1897. DOI: 10.1109/Jssc.2020.2992886  0.414
2020 Yin S, Jiang Z, Seo J, Seok M. XNOR-SRAM: In-Memory Computing SRAM Macro for Binary/Ternary Deep Neural Networks Ieee Journal of Solid-State Circuits. 55: 1733-1743. DOI: 10.1109/Jssc.2019.2963616  0.439
2019 Seo J, Cao Y, Li X, Whatmough PN. Guest Editors’ Introduction: Hardware and Algorithms for Energy-Constrained On-Chip Machine Learning (Part 2) Acm Journal On Emerging Technologies in Computing Systems. 15: 1-2. DOI: 10.1145/3359336  0.327
2019 Seo J, Cao Y, Li X, Whatmough P. Guest Editors’ Introduction to the Special Section on Hardware and Algorithms for Energy-Constrained On-chip Machine Learning Acm Journal On Emerging Technologies in Computing Systems. 15: 1-2. DOI: 10.1145/3322433  0.322
2019 Kim M, Mohanty A, Kadetotad D, Wei L, He X, Cao Y, Seo J. A Real-Time 17-Scale Object Detection Accelerator With Adaptive 2000-Stage Classification in 65 nm CMOS Ieee Transactions On Circuits and Systems I-Regular Papers. 66: 3843-3853. DOI: 10.1109/Tcsi.2019.2921714  0.384
2019 Yin S, Seo J, Kim Y, Han X, Barnaby H, Yu S, Luo Y, He W, Sun X, Kim J. Monolithically Integrated RRAM- and CMOS-Based In-Memory Computing Optimizations for Efficient Deep Learning Ieee Micro. 39: 54-63. DOI: 10.1109/Mm.2019.2943047  0.466
2019 Yin S, Kim M, Kadetotad D, Liu Y, Bae C, Kim SJ, Cao Y, Seo J. A 1.06-$\mu$ W Smart ECG Processor in 65-nm CMOS for Real-Time Biometric Authentication and Personal Cardiac Monitoring Ieee Journal of Solid-State Circuits. 54: 2316-2326. DOI: 10.1109/Jssc.2019.2912304  0.323
2019 Chen C, Murmann B, Seo J, Yoo H. Custom Sub-Systems and Circuits for Deep Learning: Guest Editorial Overview Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 9: 247-252. DOI: 10.1109/Jetcas.2019.2918317  0.345
2018 Thakur CS, Molin JL, Cauwenberghs G, Indiveri G, Kumar K, Qiao N, Schemmel J, Wang R, Chicca E, Olson Hasler J, Seo JS, Yu S, Cao Y, van Schaik A, Etienne-Cummings R. Large-Scale Neuromorphic Spiking Array Processors: A Quest to Mimic the Brain. Frontiers in Neuroscience. 12: 891. PMID 30559644 DOI: 10.3389/Fnins.2018.00891  0.359
2018 Chang K, Kadetotad D, Cao Y, Seo J, Lim SK. Power, Performance, and Area Benefit of Monolithic 3D ICs for On-Chip Deep Neural Networks Targeting Speech Recognition Acm Journal On Emerging Technologies in Computing Systems. 14: 1-19. DOI: 10.1145/3273956  0.403
2018 Ma Y, Cao Y, Vrudhula S, Seo J. Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 26: 1354-1367. DOI: 10.1109/Tvlsi.2018.2815603  0.395
2018 D'Angelo R, Du X, Salthouse CD, Hollosi B, Freifeld G, Uy W, Huang H, Tran N, Chery A, Seo J, Cao Y, Poppe DC, Sonkusale SR. Process Scalability of Pulse-Based Circuits for Analog Image Convolution Ieee Transactions On Circuits and Systems I: Regular Papers. 65: 2929-2938. DOI: 10.1109/Tcsi.2018.2821691  0.374
2018 Basu A, Acharya J, Karnik T, Liu H, Li H, Seo J, Song C. Low-Power, Adaptive Neuromorphic Systems: Recent Progress and Future Directions Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 8: 6-27. DOI: 10.1109/Jetcas.2018.2816339  0.373
2018 Basu A, Chang M, Chicca E, Karnik T, Li H, Seo J. Guest Editorial Low-Power, Adaptive Neuromorphic Systems: Devices, Circuit, Architectures and Algorithms Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 8: 1-5. DOI: 10.1109/Jetcas.2018.2810399  0.364
2018 Ma Y, Suda N, Cao Y, Vrudhula S, Seo J. ALAMO: FPGA acceleration of deep learning algorithms with a modularized RTL compiler Integration. 62: 14-23. DOI: 10.1016/J.Vlsi.2017.12.009  0.412
2017 Li J, Seo J, Kymissis I, Seok M. Triple-Mode, Hybrid-Storage, Energy Harvesting Power Management Unit: Achieving High Efficiency Against Harvesting and Load Power Variabilities Ieee Journal of Solid-State Circuits. 52: 2550-2562. DOI: 10.1109/Jssc.2017.2715827  0.373
2017 Xu Z, Skorheim S, Tu M, Berisha V, Yu S, Seo J, Bazhenov M, Cao Y. Improving efficiency in sparse learning with the feedforward inhibitory motif Neurocomputing. 267: 141-151. DOI: 10.1016/J.Neucom.2017.05.016  0.334
2016 Suda N, Chandra V, Dasika G, Mohanty A, Ma Y, Vrudhula S, Seo JS, Cao Y. Throughput-optimized openCL-based FPGA accelerator for large-scale convolutional neural networks Fpga 2016 - Proceedings of the 2016 Acm/Sigda International Symposium On Field-Programmable Gate Arrays. 16-25. DOI: 10.1145/2847263.2847276  0.325
2016 Kulkarni N, Yang J, Seo JS, Vrudhula S. Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. DOI: 10.1109/Tvlsi.2016.2527783  0.406
2016 Bang S, Seo Js, Chang L, Blaauw D, Sylvester D. A Low Ripple Switched-Capacitor Voltage Regulator Using Flying Capacitance Dithering Ieee Journal of Solid-State Circuits. DOI: 10.1109/Jssc.2015.2507361  0.566
2015 Gao L, Wang IT, Chen PY, Vrudhula S, Seo JS, Cao Y, Hou TH, Yu S. Fully parallel write/read in resistive synaptic array for accelerating on-chip learning. Nanotechnology. 26: 455204. PMID 26491032 DOI: 10.1088/0957-4484/26/45/455204  0.395
2015 Seo JS, Seok M. Digital CMOS neuromorphic processor design featuring unsupervised online learning Ieee/Ifip International Conference On Vlsi and System-On-Chip, Vlsi-Soc. 2015: 49-51. DOI: 10.1109/VLSI-SoC.2015.7314390  0.306
2015 Seo JS, Lin B, Kim M, Chen PY, Kadetotad D, Xu Z, Mohanty A, Vrudhula S, Yu S, Ye J, Cao Y. On-Chip Sparse Learning Acceleration With CMOS and Resistive Synaptic Devices Ieee Transactions On Nanotechnology. 14: 969-979. DOI: 10.1109/Tnano.2015.2478861  0.435
2015 Kadetotad D, Xu Z, Mohanty A, Chen PY, Lin B, Ye J, Vrudhula S, Yu S, Cao Y, Seo Js. Parallel Architecture With Resistive Crosspoint Array for Dictionary Learning Acceleration Ieee Journal On Emerging and Selected Topics in Circuits and Systems. DOI: 10.1109/Jetcas.2015.2426495  0.419
2014 Kadetotad D, Xu Z, Mohanty A, Chen PY, Lin B, Ye J, Vrudhula S, Yu S, Cao Y, Seo JS. Neurophysics-inspired parallel architecture with resistive crosspoint array for dictionary learning Ieee 2014 Biomedical Circuits and Systems Conference, Biocas 2014 - Proceedings. 536-539. DOI: 10.1109/BioCAS.2014.6981781  0.305
2014 Xu Z, Mohanty A, Chen PY, Kadetotad D, Lin B, Ye J, Vrudhula S, Yu S, Seo JS, Cao Y. Parallel programming of resistive cross-point array for synaptic plasticity Procedia Computer Science. 41: 126-133. DOI: 10.1016/J.Procs.2014.11.094  0.304
2013 Rajendran B, Liu Y, Seo JS, Gopalakrishnan K, Chang L, Friedman DJ, Ritter MB. Specifications of nanoscale devices and circuits for neuromorphic computational systems Ieee Transactions On Electron Devices. 60: 246-253. DOI: 10.1109/Ted.2012.2227969  0.365
2011 Seo JS, Kaul H, Krishnamurthy R, Sylvester D, Blaauw D. A robust edge encoding technique for energy-efficient multi-cycle interconnect Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 19: 264-273. DOI: 10.1109/Tvlsi.2009.2032422  0.638
2011 Seo JS, Blaauw D, Sylvester D. Crosstalk-aware PWM-based on-chip links with self-calibration in 65 nm CMOS Ieee Journal of Solid-State Circuits. 46: 2041-2052. DOI: 10.1109/Jssc.2011.2136630  0.589
2009 Lee J, Kang J, Park S, Seo J, Anders J, Guilherme J, Flynn MP. A 2.5 mW 80 dB DR 36 dB SNDR 22 MS/s Logarithmic Pipeline ADC Ieee Journal of Solid-State Circuits. 44: 2755-2765. DOI: 10.1109/Jssc.2009.2028052  0.338
2008 Singh P, Seo JS, Blaauw D, Sylvester D. Self-timed regenerators for high-speed and low-power on-chip global interconnect Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 16: 673-677. DOI: 10.1109/Tvlsi.2008.2000250  0.557
2008 Kaul H, Seo JS, Anders M, Sylvester D, Krishnamurthy R. A robust alternate repeater technique for high performance busses in the multi-core era Proceedings - Ieee International Symposium On Circuits and Systems. 372-375. DOI: 10.1109/ISCAS.2008.4541432  0.564
2008 Seok M, Hanson S, Seo JS, Sylvester D, Blaauw D. Robust ultra-low voltage ROM design Proceedings of the Custom Integrated Circuits Conference. 423-426. DOI: 10.1109/CICC.2008.4672110  0.31
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