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Marcin Rogawski, Ph.D. - Publications

Affiliations: 
2013 Electrical and Computer Engineering George Mason University, Washington, DC 
Area:
Computer Engineering
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8 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2014 Rogawski M, Homsirikamol E, Gaj K. A novel modular adder for one thousand bits and more using fast carry chains of modern FPGAs Conference Digest - 24th International Conference On Field Programmable Logic and Applications, Fpl 2014. DOI: 10.1109/FPL.2014.6927493  0.589
2013 Rogawski M, Gaj K, Homsirikamol E. A high-speed unified hardware architecture for 128 and 256-bit security levels of AES and the SHA-3 candidate Grøstl Microprocessors and Microsystems. 37: 572-582. DOI: 10.1016/J.Micpro.2013.05.005  0.63
2012 Rogawski M, Gaj K. A high-speed unified hardware architecture for AES and the SHA-3 candidate Grøstl Proceedings - 15th Euromicro Conference On Digital System Design, Dsd 2012. 568-575. DOI: 10.1109/DSD.2012.8  0.638
2011 Salman A, Rogawski M, Kaps JP. Efficient hardware accelerator for IPSec based on partial reconfiguration on Xilinx FPGAs Proceedings - 2011 International Conference On Reconfigurable Computing and Fpgas, Reconfig 2011. 242-248. DOI: 10.1109/ReConFig.2011.33  0.402
2011 Shahid R, Sharif MU, Rogawski M, Gaj K. Use of embedded FPGA resources in implementations of 14 round 2 SHA-3 candidates 2011 International Conference On Field-Programmable Technology, Fpt 2011. DOI: 10.1109/FPT.2011.6132680  0.624
2011 Homsirikamol E, Rogawski M, Gaj K. Throughput vs. area trade-offs in high-speed architectures of five round 3 SHA-3 candidates implemented using xilinx and altera FPGAs Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 6917: 491-506. DOI: 10.1007/978-3-642-23951-9_32  0.597
2010 Gaj K, Kwon S, Baier P, Kohlbrenner P, Le H, Khaleeluddin M, Bachimanchi R, Rogawski M. Area-time efficient implementation of the elliptic curve method of factoring in reconfigurable hardware for application in the number field sieve Ieee Transactions On Computers. 59: 1264-1280. DOI: 10.1109/Tc.2009.191  0.619
2010 Gaj K, Homsirikamol E, Rogawski M. Fair and comprehensive methodology for comparing hardware performance of fourteen round two SHA-3 candidates using FPGAs Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 6225: 264-278. DOI: 10.1007/978-3-642-15031-9_18  0.59
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