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Peiyi Zhao, Ph.D. - Publications

Affiliations: 
2005 University of Louisiana at Lafayette, Lafayette, LA, United States 
Area:
Electronics and Electrical Engineering, Computer Science
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6 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2019 Samiee A, Borulkar P, DeMara RF, Zhao P, Bai Y. Low-Energy Acceleration of Binarized Convolutional Neural Networks using a Spin Hall Effect based Logic-in-Memory Architecture Ieee Transactions On Emerging Topics in Computing. 1-1. DOI: 10.1109/Tetc.2019.2915589  0.341
2011 Zhao P, McNeely J, Kuang W, Wang N, Wang Z. Design of Sequential Elements for Low Power Clocking System Ieee Transactions On Very Large Scale Integration Systems. 19: 914-918. DOI: 10.1109/Tvlsi.2009.2038705  0.688
2010 Kuang W, Zhao P, Yuan JS, DeMara RF. Design of asynchronous circuits for high soft error tolerance in deep submicrometer CMOS circuits Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 18: 410-422. DOI: 10.1109/Tvlsi.2008.2011554  0.388
2009 Zhao P, McNeely JB, Golconda PK, Venigalla S, Wang N, Bayoumi MA, Kuang W, Downey L. Low-power clocked-pseudo-NMOS flip-flop for level conversion in dual supply systems Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 17: 1196-1202. DOI: 10.1109/Tvlsi.2008.2002426  0.663
2007 Zhao P, McNeely J, Golconda P, Bayoumi MA, Barcenas RA, Kuang W. Low-Power Clock Branch Sharing Double-Edge Triggered Flip-Flop Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 15: 338-345. DOI: 10.1109/Tvlsi.2007.893623  0.671
2004 Zhao P, Darwish TK, Bayoumi MA. High-performance and low-power conditional discharge flip-flop Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 12: 477-484. DOI: 10.1109/Tvlsi.2004.826192  0.647
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